Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

429

This register contains the base address of Graphics Data Stolen DRAM memory. Note : 

IVB located this register in device 0, 0xB0. Mirrored into device 2, 0x5C.Graphics 

Stolen Memory is within DRAM space. The base of stolen memory will always be below 

4G.

Default: 00000000h

7:3

00101b

RW/L

Graphics Mode Select (GMS). This field is used to select the amount of 

Main Memory that is pre-allocated to support the Internal Graphics device in VGA (non-

linear) and Native (linear) modes. The BIOS ensures that memory is pre-allocated only 

when Internal graphics is enabled. Hardware does not clear or set any of these bits 

automatically based on IGD being disabled/enabled. BIOS Requirement: BIOS must not 

set this field to 0h if IVD (bit 1 of this register) is 0. 0h = 0MB 10h = 512MB 1h = 32MB 

2h = 64MB 3h = 96MB 4h = 128MB 5h = 160MB 6h = 192MB 7h = 224MB 8h = 256MB 

9h = 288MB Ah = 320MB Bh = 352MB Ch = 384MB Dh = 416MB Eh = 448MB Fh = 

480MB Other = Reserved When GMS != 000 (and VD=0): Address[31:0] is compared 

with VGA memory range. (The VGA memory range is A_0000h to B_FFFFh.). If there is 

a match and MSE = 1 and MEMRD or MEMWR, the access will route as a 

Rmdwvgamemen_cr cycle on the RMbus. If the RMbus returns a hit the GVD will select 

the command. As well, when 0 the GVD will check if scldown3_address[15:0] is one of 

the VGA IO register range. (The VGA IO range is 03B0h - 03BBh and 03C0h - 03DFh.) If 

there is a match and IOSE = 1 and the SCL command is either an IORD or IOWR, the 

GVD will intiate a (VGA) register cycle on the RMbus. If the RMbus returns a hit the GVD 

will select the command When GMS == 000 : No address compare will occur against 

VGA memory range or the VGA IO register range. Also, CC[15:8] is changed to 8?h80 

from 8'h00

2

0b

RO

Reserved

1

0b

RW/L

VGA Disable (VD): 0: Enable. Device 2 (IGD) 

claims VGA memory and IO cycles, the Sub-Class Code within Device 2 Class Code 

register is 00. 1: Disable. Device 2 (IGD) does not claim VGA cycles (Mem and IO), and 

the Sub- Class Code field within Device 2 function 0 Class Code register is 80. BIOS 

Requirement: BIOS must not set this bit to 0 if the GMS field pre-allocates no memory. 

This bit MUST be set to 1 if Device 2 is disabled either via a fuse or fuse override 

(CAPID0[38] = 1) or via a register (DEVEN[3] = 0).

0

0b

RW/L

When set to 1b, this bit will lock all bits in this register.

PCI Configuration Register

(Size: 32 bits)

Core

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BDS

M

_0

RSVD

_1

BDSM_L

O

C

K

_

2