Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

433

Default: 0000B005h

Message Address.SOXi Context Save/Restore : Yes

PCI Configuration Register

(Size: 32 bits)

Core

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1

R

SVD_2

ADD

R

ES

S_64_BIT_CAP

ABLE_3

MU

LT

IPLE

_M

E

S

S

A

GE_E

N

A

BLE_4

MUL

T

IP

LE_MES

S

A

G

E_C

A

PA

BLE_5

MSI_E

N

ABLE_6

POINTE

R_T

O

_NEX

T_CA

PA

BILITY_0

CA

PA

BI

LI

TY_

ID_

1

31:24

00h

RO

Reserved

23

0b

RO

C64: 32-bit 

capable only

22:20

000b

RW

MME: This 

field is RW for software compatibility, but only a single message is ever generated. 

System software programs this field to indicate the actual number of messages 

allocated to this device. This number will be equal to or less than the number actually 

requested. The encoding is the same as for the MMC field below.

19:17

000b

RO

MMC: This 

device is only single message capable System Software reads this field to determine the 

number of messages being requested by this device. Value: Number of requests 000: 1. 

001- 111: Reserved

16

0b

RW

MSIE: If set, MSI is enabled and traditional 

interrupts are not used to generate interrupts. PCICMDSTS.BME must be set for an MSI 

to be generated. 0 : MSI interrupts are disabled. 1 : MSI interrupts are enabled. Permits 

sending an MSI interrupt.

15:8

B0h

RW/O

Points 

to the next item in the list (B0=VCID support). This register should be programmed by 

BIOS during boot-up. Once written, this register becomes Read_Only. This register can 

only be cleared by a Reset.

7:0

05h

RO

CAPID: Indicates an MSI capability

PCI Configuration Register

(Size: 32 bits)

Core