Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

439

Power Management Control/Status. Driver doesn't use this register. SBIOS doesn't use 

this register SOXi Context Save/Restore : Yes.

Default: 00000000h

Software SMI or SCI.To generate a SW SMI event, software should program bit 15:0 

and trigger SMI. Note : ILK/SNB/IVB had SCI and SMI separated (E0 and E8) As long 

as there is the potential that DVO port legacy drivers exist which expect this register at 

this address, this must be reserved for this register. The SCI mechanism for driver / 

BIOS communication. SMI is a system wide lock interrupt (halts the all the cores) as 

opposed to SCI. Vista and Win7 recommend to use the SCI. The SMI is slowly being 

phased out. This register serves 2 purposes: 1) Support selection of SMI or SCI event 

source (SMISCISEL - bit15) 2) Event trigger (bit 0). To generate a SW SCI event, 

software (System BIOS/Graphics driver) should program bit 15 (SMISCISEL) to 1. This 

is typically programmed once (assuming SMIs are never triggered). On a ?0? to ?1? 

subsequent transition in bit 0 of this register (caused by a software write operation), 

GMCH sends a single SCI message. The SCI will set the DMISCI bit in its TCO1_STS 

register and TCOSCI_STS bit in its GPE0 register upon receiving this message from 

DMI. Once written as 1, software must write a ?0? to this bit to clear it, and all other 

write transitions (1-)0, 0-)0, 1-)1) or if bit 15 is ?0? will not cause GMCH to send SCI 

message to DMI link. To generate a SW SMI event, software should program bit 15 to 0 

and trigger an SMI.

PCI Configuration Register

(Size: 32 bits)

Core

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD_0

PO

WE

R_S

TA

T

E

_

PS

_1

31:2

00000000h

RO

Reserved

1:0

00b

RW

This field indicates the current power 

state of the IGD and can be used to set the IGD into a new power state. If software 

attempts to write an unsupported state to this field, write operation must complete 

normally on the bus, but the data is discarded and no state change occurs. On a 

transition from D3 to D0 the graphics controller is optionally reset to initial values. 

Behavior of the graphics controller in supported states is detailed in the power 

management section of the Bspec. Bits[1:0] Power state 00: D0 Default 01: D1 Not 

Supported 10: D2 Not Supported 11: D3 Signal : gvd_dsp_power_state_d3_zncznfwoh 

output to 2D.