Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
440
Datasheet
Access Method
Default: 00000000h
14.9.29
ASLE—Offset E4h
System Display Event Register. SBIOS writes this reg to generate interrupt to graphics/
display driver.
Access Method
Default: 00000000h
Type:
PCI Configuration Register
(Size: 32 bits)
Power Well:
Core
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD_0
SMI_OR_SCI_EVE
NT_SE
LECT_1
SOF
T
W
A
RE
_SCRA
TC
H
_BIT
S_2
SMI_OR_SCI_EVENT_3
Bit
Range
Default &
Access
Description
31:16
0000h
RO
RSVD (RSVD_0):
Reserved
15
0b
RW
SMI_OR_SCI_EVENT_SELECT (SMI_OR_SCI_EVENT_SELECT_1):
MCS: SMI or
SCI event select. 0 = SMI,1 = SCI
14:1
0000h
RW
SOFTWARE_SCRATCH_BITS (SOFTWARE_SCRATCH_BITS_2):
Used by driver to
communicate information to SBIOS
0
0b
RW
SMI_OR_SCI_EVENT (SMI_OR_SCI_EVENT_3):
MCE:MCS=1, setting this bit
causes an SCI. MCS=0, setting this bit causes an SMI. A 1 to 0, 0 to 0 or 1 to 1
transition of this bit does not trigger any events. The graphics driver writes to this
register as a means to interrupt the SBIOS
Type:
PCI Configuration Register
(Size: 32 bits)
Power Well:
Core