Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
442
Datasheet
14.9.31
ASLS—Offset FCh
ASL Storage. The Valleyview display driver does not need this register since memory
Operational Region (OpRegion) is available. This register is kept for use as scratch
space. SOXi Context Save/Restore : Yes This software scratch register only needs to be
read/write accessible. The exact bit register usage must be worked out in common
between System BIOS and driver software, but storage for switching/indicating up to 6
devices is possible with this amount. For each device, the ASL control method with
require two bits for _DOD (BIOS detectable yes or no, VGA/NonVGA), one bit for _DGS
(enable/disable requested), and two bits for _DCS (enabled now/disabled now,
connected or not).
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
_0
S
T
E
PPING_I
D_1
MAN
U
FA
CTURING_I
D
_2
Bit
Range
Default &
Access
Description
31:24
00h
RO
RSVD (RSVD_0):
Reserved
23:16
00000000b
RO
Stepping_ID (STEPPING_ID_1):
Hardwired to strapRID[7:0] via top level
metal.23:16 - Manufacturing Stepping ID (00 = A0)
15:0
0000h
RO
MANUFACTURING_ID (MANUFACTURING_ID_2):
Hardwired to strapMANID[15:0]
via top level metal. 15:8 - Foundry (0Fh = Intel, Others = Reserved) 7:3 - Fab process
12h : Fab code for P1263 13h : P1264 14h : P1265 15h : P1266 ... 1Ah : P1271 (VV
POR) Others : Reserved 2:0 - Identifies the dot process 000 = Code for 0 001 = Code
for .1 (VV POR) 010 = Code for .2 110 = Code for .4 011 = Code for .7
Type:
PCI Configuration Register
(Size: 32 bits)
ASLS:
Power Well:
Core
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SC
RA
TC
H
_
0