Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

Datasheet

445

14.10

Memory Mapped Registers (1 of 2)

Table 170.

Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default Value

3B4–3B4h

1

“CRX (CRX_MDA)—Offset 3B4h” on page 450

00h

3B5–3B5h

1

“CR (CR_MDA)—Offset 3B5h” on page 451

00h

3C0–3C0h

1

“ARX—Offset 3C0h” on page 452

00h

3C1–3C1h

1

“ARX—Offset 3C0h” on page 452

00h

3C4–3C4h

1

“SRX—Offset 3C4h” on page 453

00h

3C5–3C5h

1

“SRX—Offset 3C4h” on page 453

00h

3C6–3C6h

1

“DACMASK—Offset 3C6h” on page 454

00h

3C8–3C8h

1

“DACWX—Offset 3C8h” on page 455

00h

3C9–3C9h

1

“DACDATA—Offset 3C9h” on page 455

00h

3CA–3CAh

1

“FCR (FCR_Read)—Offset 3CAh” on page 456

00h

3CC–3CCh

1

“MSR (MSR_READ)—Offset 3CCh” on page 457

00h

3CE–3CEh

1

“GRX—Offset 3CEh” on page 458

00h

3CF–3CFh

1

“GRX—Offset 3CEh” on page 458

00h

3D4–3D4h

1

“CRX (CRX_CGA)—Offset 3D4h” on page 460

00h

3D5–3D5h

1

“CR (CR_CGA)—Offset 3D5h” on page 460

00h

5010–5013h

4

“GPIOCTL_0—Offset 5010h” on page 461

00000808h

5014–5017h

4

“GPIOCTL_1—Offset 5014h” on page 463

00000808h

5018–501Bh

4

“GPIOCTL_2—Offset 5018h” on page 464

00000808h

501C–501Fh

4

“GPIOCTL_3—Offset 501Ch” on page 466

00000808h

5020–5023h

4

“GPIOCTL_4—Offset 5020h” on page 468

00000808h

5100–5103h

4

“GMBUS0—Offset 5100h” on page 470

00000000h

5104–5107h

4

“GMBUS1—Offset 5104h” on page 471

00000000h

5108–510Bh

4

“GMBUS2—Offset 5108h” on page 473

00000800h

510C–510Fh

4

“GMBUS3—Offset 510Ch” on page 475

00000000h

5110–5113h

4

“GMBUS4—Offset 5110h” on page 476

00000000h

5120–5123h

4

“GMBUS5—Offset 5120h” on page 477

00000000h

5130–5133h

4

“GMBUS6—Offset 5130h” on page 477

00000000h

5134–5137h

4

“GMBUS7—Offset 5134h” on page 478

00000000h

6014–6017h

4

“DPLLA_CTRL—Offset 6014h” on page 479

00002000h

6018–601Bh

4

“DPLLB_CTRL—Offset 6018h” on page 481

00006000h

601C–601Fh

4

“DPLLAMD—Offset 601Ch” on page 484

00000003h

6020–6023h

4

“DPLLBMD—Offset 6020h” on page 486

00000003h

6024–6027h

4

“RAWCLK_FREQ—Offset 6024h” on page 487

0000007Dh

6104–6107h

4

“D_STATE—Offset 6104h” on page 488

20D00400h

6200–6203h

4

“DSPCLK_GATE_D—Offset 6200h” on page 489

10000000h

6204–6207h

4

“DPPSR_CGDIS—Offset 6204h” on page 492

00000200h