Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

Datasheet

447

B074–B077h

4

“MIPIA_GEN_FIFO_STAT_REGISTER—Offset B074h” on page 531

1E060606h

B078–B07Bh

4

“MIPIA_HS_LS_DBI_ENABLE_REG—Offset B078h” on page 533

00000000h

B07C–B07Fh

4

“MIPIA_RESERVED—Offset B07Ch” on page 533

00000000h

B080–B083h

4

“MIPIA_DPHY_PARAM_REG—Offset B080h” on page 534

0B061A04h

B084–B087h

4

“MIPIA_DBI_BW_CTRL_REG—Offset B084h” on page 535

00000000h

B088–B08Bh

4

“MIPIA_CLK_LANE_SWITCHING_TIME_CNT—Offset B088h” on

00000000h

B08C–B08Fh

4

“MIPIA_STOP_STATE_STALL—Offset B08Ch” on page 536

00000000h

B090–B093h

4

“MIPIA_INTR_STAT_REG_1—Offset B090h” on page 537

00000000h

B094–B097h

4

“MIPIA_INTR_EN_REG_1—Offset B094h” on page 537

00000000h

B100–B103h

4

“MIPIA_DBI_TYPEC_CTRL—Offset B100h” on page 538

00000000h

B104–B107h

4

“MIPIA_CTRL—Offset B104h” on page 539

00000000h

B108–B10Bh

4

“MIPIA_DATA_ADD—Offset B108h” on page 540

00000000h

B10C–B10Fh

4

“MIPIA_DATA_LEN—Offset B10Ch” on page 540

00000000h

B110–B113h

4

“MIPIA_CMD_ADD—Offset B110h” on page 541

00000000h

B114–B117h

4

“MIPIA_CMD_LEN—Offset B114h” on page 542

00000000h

B118–B11Bh

4

“MIPIA_RD_DATA_RETURN0—Offset B118h” on page 542

00000000h

B11C–B11Fh

4

“MIPIA_RD_DATA_RETURN1—Offset B11Ch” on page 543

00000000h

B120–B123h

4

“MIPIA_RD_DATA_RETURN2—Offset B120h” on page 544

00000000h

B124–B127h

4

“MIPIA_RD_DATA_RETURN3—Offset B124h” on page 544

00000000h

B128–B12Bh

4

“MIPIA_RD_DATA_RETURN4—Offset B128h” on page 545

00000000h

B12C–B12Fh

4

“MIPIA_RD_DATA_RETURN5—Offset B12Ch” on page 545

00000000h

B130–B133h

4

“MIPIA_RD_DATA_RETURN6—Offset B130h” on page 546

00000000h

B134–B137h

4

“MIPIA_RD_DATA_RETURN7—Offset B134h” on page 547

00000000h

B138–B13Bh

4

“MIPIA_RD_DATA_VALID—Offset B138h” on page 547

00000000h

B800–B803h

4

“MIPIC_DEVICE_READY_REG—Offset B800h” on page 548

00000000h

B804–B807h

4

“MIPIC_INTR_STAT_REG—Offset B804h” on page 548

00000000h

B808–B80Bh

4

“MIPIC_INTR_EN_REG—Offset B808h” on page 550

00000000h

B80C–B80Fh

4

“MIPIC_DSI_FUNC_PRG__REG—Offset B80Ch” on page 552

00000001h

B810–B813h

4

“MIPIC_HS_TX_TIMEOUT_REG—Offset B810h” on page 553

00000000h

B814–B817h

4

“MIPIC_LP_RX_TIMEOUT_REG—Offset B814h” on page 554

00000000h

B818–B81Bh

4

“MIPIC_TURN_AROUND_TIMEOUT_REG—Offset B818h” on page 555

00000000h

B81C–B81Fh

4

“MIPIC_DEVICE_RESET_TIMER—Offset B81Ch” on page 556

00000000h

B820–B823h

4

“MIPIC_DPI_RESOLUTION_REG—Offset B820h” on page 556

00000000h

B824–B827h

4

“MIPIC_DBI_RESOLUTION_REG—Offset B824h” on page 557

00000000h

B828–B82Bh

4

“MIPIC_HORIZ_SYNC_PADDING_COUNT—Offset B828h” on page 557

00000000h

B82C–B82Fh

4

“MIPIC_HORIZ_BACK_PORCH_COUNT—Offset B82Ch” on page 558

00000000h

B830–B833h

4

“MIPIC_HORIZ_FRONT_PORCH_COUNT—Offset B830h” on page 559

00000000h

B834–B837h

4

“MIPIC_HORIZ_ACTIVE_AREA_COUNT—Offset B834h” on page 560

00000000h

Table 170.

Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default Value