Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
455
14.10.8
DACWX—Offset 3C8h
Palette Write Index Register
Access Method
Default: 00h
14.10.9
DACDATA—Offset 3C9h
Palette Data Register
Access Method
Default: 00h
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0b
RW
PIXEL_DATA_MASK:
In indexed-color mode, the 8 bits of this register are logically
ANDed with the 8 bits of pixel data received from the frame buffer for each pixel. The
result of this ANDing process becomes the actual index used to select color data
positions within the palette. This has the effect of limiting the choice of color data
positions that may be specified by the incoming 8-bit data.
0 = Corresponding bit in the resulting 8-bit index being forced to 0.
1 = Allows the corresponding bit in the resulting index to reflect the actual value of the
corresponding bit in the incoming 8-bit pixel data.
Type:
Memory Mapped I/O Register
(Size: 8 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
PA
LE
TT
E
_
W
R
IT
E
_
IN
D
E
X
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0b
WO
PALETTE_WRITE_INDEX:
The 8-bit index value programmed into this register
chooses which of 256 standard color data positions within the palette are to be made
accessible for being written via the Palette Data Register (DACDATA). The index value
held in this register is automatically incremented when all three bytes of the color data
position selected by the current index have been written. This register allows access to
the palette even when running non-VGA display modes.
Type:
Memory Mapped I/O Register
(Size: 8 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h