Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

470

Datasheet

GMBUS Clock/Port Select gmbus clock and port select (gmbus_register.v reg_gmbus0)

Default: 00000000h

0

0b

WO

This is a mask bit to determine whether the 

GPIO Clock DIRECTION VALUE bit should be written into the register. This value is not 

stored and when read returns 0. 

0 = Do NOT update the GPIO Clock Direction Value bit on a write (default). 

1 = Update the GPIO Clock Direction Value bit. on a write operation to this register.  

AccessType: Write Only

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RES

E

RVE

D

H

O

LD_TIME_EXTEN

S

ION

RES

E

RV

ED_1

A

K

SV

_BUFFE

R_SE

LEC

T

GMBUS

_

RA

TE

_S

ELE

C

T

RES

E

RV

ED_2

PIN_P

A

IR_S

ELE

C

T

31:16

0b

RW

Reserved.

15

0b

RW

This bit selects the hold time on the data line driven from 

the GMCH. 

0 = Hold time of 0ns 

1 = Hold time of 300 ns

14:12

0b

RW

Reserved.

11

0b

RW

[DevBLC, DevCTG, DevCDV] This bit selects whether the 

data to be written over GMBUS comes from the Aksv buffer for HDCP authentication, or 

from the GMBUS data buffer. Please note that when writing data from the Aksv buffer, 

all GMBUS protocol must be followed, including indicating the number of bytes to be 

transferred during the DATA phase of a GMBUS cycle. 

0 (Default) Use the GMBUS data buffer (GMBUS3) for data transmission 

1 Use the Aksv data buffer (GMBUS6 and GMBUS7) for data transmission. 

[DevBW, DevCL] Reserved: