Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
479
14.10.29 DPLLA_CTRL—Offset 6014h
DPLL A Control Register DPLL A Control (cpdmmreg.v reg03_lt)
Access Method
Default: 00002000h
Bit
Range
Default &
Access
Field Name (ID): Description
31:9
0b
WO
RESERVED:
MBZ
8
0b
WO
AKSV_SELECTION_BIT:
[DevVLVP]:
•
0 = The fuse value of the Aksv is used.
•
1 = The register value of the Aksv is used.
Aksv Selection Bit [DevELK, DevCDV]:
•
•
0 = The register value of the Aksv is used.
•
1 = The fuse value of the Aksv is used. [DevBLC, DevCTG] Reserved
7:0
0b
WO
DATA_BYTE_5:
gmbus data buffer DATA Byte 5
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
DPLL_A_V
C
O
_
E
N
ABLE
DPLLA
_EXTE
R
NAL_CL
OCK_BUFFE
R_
E
N
ABLE
REF
A
_CL
O
C
K
_
E
NABLE
VG
A
_
MO
DE_DIS
ABLE
ENABLE
_SING
LE_DP
LLA
_
FREQUENC
Y
_FO
R
_BO
T
H
_
PI
PE
S
RESE
RVED
RESE
RVE
D
_1
RESE
RVE
D
_2
VC
C
_
VOL
TAG
E
_
SELE
CT
DP
LL
_A_REFE
R
ENCE_INPU
T
_SELE
C
T
RESE
RVE
D
_3
DIS
PLA
Y
_
RA
TE_S
WIT
C
H_
PIPE
A
DP
IO_
PHY
S
TA
T
US
_
R
E
A
D
_
O
N
LY
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
DPLL_A_VCO_ENABLE:
Disabling the PLLA will cause the display dot clock to stop.
0 = DPLLA is disabled in its lowest power state (default)
1 = DPLLA is enabled and operational (42usec until lock without calibration and 110usec
for calibration)