Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

489

Clock Gating Disable for Display Register clock gating (cpdmmreg.v reg12_lt)

Default: 10000000h

15

0b

RW

: MBZ

14:8

0000100b

RW

(DevCDV): 

This is the minimum time required the DPLL to be power down until it is allowed to turn 

it on again. The HW counter using HRAW clk (5nsec) and has resolution of 160nsec 

(SEG DPLL required time is 0.5usec)

7:4

0b

RW

: MBZ

3

0b

RW

This bit determines whether the PCI 

Power State Powers down the Dot Clock PLLs when in D3. A 0 on this bit does not power 

down the DPLLs, requiring software to gate them if necessary. When this bit is a 1, the 

dot PLLs are powered down when in D3. The PCI power state is determined by bits 1:0 

of the PCI Power Management Control/Status register.

2

0b

RW

Reserved.

1

0b

RW

[DevCDV] 

Graphics Core Clock Gating: This bit determines whether the PCI Power State gates the 

Graphics Core clocks when in the D3 state. A 0 on this bit does not gate the clocks, 

requiring software to gate them if necessary. When this bit is a 1, the graphics core 

clocks are gated at the outputs of the PLLs when in D3. The PCI power state is 

determined by bits 1:0 of the PCI Power Management Control/Status register.  

This register field has no use in current products.

0

0b

RW

This bit determines whether the PCI Power State gates the Dot 

clocks when in the D3 state. A 0 on this bit does not gate the clocks, requiring software 

to gate them if necessary. When this bit is a 1, the dot clocks are gated at the outputs of 

the PLLs when in D3. The PCI power state is determined by bits 1:0 of the PCI Power 

Management Control/Status register.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h