Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
490
Datasheet
31
28
24
20
16
12
8
4
0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HD
CP
UNIT_CLO
CK
_GA
T
ING_D
IS
A
BLE
D
P
UNIT_PIPEB_CL
O
CK_GA
T
ING_DIS
A
BLE
VSUNIT_PIPE_A_CL
O
CK_GA
T
ING_DIS
A
BLE
V
R
HUNIT_CL
OCK_GA
TING_DIS
ABLE
VRDUNIT_CL
OCK_GA
TING_DIS
ABLE
A
U
DUNIT_CL
OCK_GA
TING_DIS
ABLE
DPUNIT_PIP
E
A
_CL
O
CK_GA
T
ING_DIS
A
BLE
DPCUNIT_CL
OCK_GA
TING_DIS
ABLE
VSU
N
IT_PIPE_B_CL
OCK_GA
TING_DIS
ABLE
SP
RIT
E
_D_CL
O
CK_GA
T
ING_DIS
A
BLE
SPRITE
_
C
_CL
O
CK_GA
T
ING_DIS
A
BLE
SP
R
IT
E
_B_CL
O
CK_GA
T
ING_DIS
A
BLE
DVSUNIT_SPRIT
E
_A_CL
O
CK_GA
T
ING_DIS
A
BLE
DDBUNIT_CL
OCK_GA
TING_DIS
ABLE
GMBUSUNIT_CL
OCK_GA
TING_DIS
ABLE
D
P
RUNIT_CL
OCK_GA
TING_DIS
ABLE
D
P
FUNIT_CL
OCK_GA
TING_DIS
ABLE
DPLRUNIT_PIPE_A_CL
OCK_GA
TING_DIS
ABLE
DPLSUNIT_PIPE_A_CL
OCK_GA
TING_DIS
ABLE
DPTUNIT_CL
OCK_GA
TING_DIS
ABLE
DP
OU
NIT_C
LOC
K_G
A
TING
_DIS
ABLE
DPBUNIT_PIPE_A_CL
O
CK_GA
T
ING_DIS
A
BLE
DC
UNIT_PIPE_A_CL
OCK_GA
TING_DIS
ABLE
DPGCU
N
IT_PIPE_B_CL
OCK_GA
TING_DIS
ABLE
DPGC
UNIT_PIPE_A_CL
OCK_GA
TING_DIS
ABLE
DPIOUNIT_CL
O
CK_GA
T
ING_DIS
A
BLE
OVFU
NIT_C
LOC
K_G
A
TING
_DIS
ABLE
OVBU
NIT_C
LOC
K_G
A
TING
_DIS
ABLE
DP
LR
U
N
IT_PIPE_B_CL
OCK_GA
TING_DIS
ABLE
DPLSU
N
IT_PIPE_B_CL
OCK_GA
TING_DIS
ABLE
D
P
B
U
NIT_PIPE_B_CL
O
CK_GA
T
ING_DIS
A
BLE
DCU
N
IT_PIPE_B_CL
OCK_GA
TING_DIS
ABLE
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
HDCPUNIT_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit enabling
logic
1 = Disable clock gating function
[DevBW]: Reserved. MBZ. This bit is not connected on [DevBW].
30
0b
RW
DPUNIT_PIPEB_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit
enabling logic
1 = Disable clock gating function
29
0b
RW
VSUNIT_PIPE_A_CLOCK_GATING_DISABLE:
[DevVLVP] (this bit used to be in PCI
space in Calistoga)
0 = Clock gating controlled by unit enabling logic
1 = Disable clock gating function
28
1b
RW
VRHUNIT_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit enabling
logicg
1 = Disable clock gating function
Clock gating should not be enabled for this unit (this bit should always be set to 1.)
[DevBW]: Reserved. MBZ. This bit is not connected on [DevBW].
27
0b
RW
VRDUNIT_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit enabling
logic
1 = Disable clock gating function
26
0b
RW
AUDUNIT_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit enabling
logic
1 = Disable clock gating function
[DevBW]: Reserved. MBZ. This bit is not connected on [DevBW].
25
0b
RW
DPUNIT_PIPEA_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit
enabling logic
1 = Disable clock gating function
24
0b
RW
DPCUNIT_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit enabling
logic
1 = Disable clock gating function
23
0b
RW
VSUNIT_PIPE_B_CLOCK_GATING_DISABLE:
[DevVLVP]
0 = Clock gating controlled by unit enabling logic
1 = Disable clock gating function
[DevBW]: Reserved. MBZ. This bit is not connected on [DevBW].
[DevCDV] and [DevVLVP]: Reserved