Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
491
22
0b
RW
SPRITE_D_CLOCK_GATING_DISABLE:
[DevVLVP]
0 = Clock gating controlled by unit enabling logic
1 = Disable clock gating function
[DevBW]: Reserved. MBZ. This bit is not connected on [DevBW].
[DevCDV]: Reserved
21
0b
RW
SPRITE_C_CLOCK_GATING_DISABLE:
[DevVLVP]
0 = Clock gating controlled by unit enabling logic
1 = Disable clock gating function
[DevBW]: Reserved. MBZ. This bit is not connected on [DevBW].
[DevCDV]: Reserved
20
0b
RW
SPRITE_B_CLOCK_GATING_DISABLE:
[DevVLVP]
0 = Clock gating controlled by unit enabling logic
1 = Disable clock gating function
[DevBW] and [DevBLC]: Reserved. MBZ. This bit is not connected on [DevBW] and
[DevBLC].
[DevCDV]: Reserved
19
0b
RW
DVSUNIT_SPRITE_A_CLOCK_GATING_DISABLE:
[DevBW] and [DevCL]
0 = Clock gating controlled by unit enabling logic
1 = Disable clock gating function
[DevBLC] and [DevCTG]: Reserved. MBZ. This bit is not connected on [DevBLC] and
[DevCTG].
18
0b
RW
DDBUNIT_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit enabling
logic
1 = Disable clock gating function
[DevCTG] Always program this bit to 1
17
0b
RW
GMBUSUNIT_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit
enabling logic
1 = Disable clock gating function
16
0b
RW
DPRUNIT_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit enabling
logic
1 = Disable clock gating function
15
0b
RW
DPFUNIT_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit enabling
logic
1 = Disable clock gating function
14
0b
RW
DPLRUNIT_PIPE_A_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit
enabling logic
1 = Disable clock gating function
[DevBW] and [DevBLC]: Reserved. MBZ. This bit is not connected on [DevBW] and
[DevBLC].
13
0b
RW
DPLSUNIT_PIPE_A_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit
enabling logic
1 = Disable clock gating function
[DevBW] and [DevBLC]: Reserved. MBZ. This bit is not connected on [DevBW] and
[DevBLC].
12
0b
RW
DPTUNIT_CLOCK_GATING_DISABLE:
[DevVLVP]
[DevCDV] Dplunit Clock Gating Disable:
0 = Clock gating controlled by unit enabling logic
1 = Disable clock gating function
[DevBW] and [DevBLC]: Reserved. MBZ. This bit is not connected on [DevBW] and
[DevBLC].
11
0b
RW
DPOUNIT_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit enabling
logic
1 = Disable clock gating function
10
0b
RW
DPBUNIT_PIPE_A_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit
enabling logic
1 = Disable clock gating function
9
0b
RW
DCUNIT_PIPE_A_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit
enabling logic
1 = Disable clock gating function
Bit
Range
Default &
Access
Field Name (ID): Description