Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
493
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
LO
W
_
PO
WE
R_S
INGLE
_P
IPE
_
A_LP
S
S
A_C
LOC
K_G
A
TING
_DIS
ABLE
LO
W_P
O
W
E
R_SING
LE_P
IP
E_B_LP
S
S
A_C
LOC
K_G
A
TING
_DIS
ABLE
RE
SE
RVED
D
P
IO_C
LO
CK_BUFFER_ENABLE_CL
O
CK_GA
T
ING_DIS
A
BLE
DISP
LA
Y_P
LA
N
E
_
A_P
S
R_C
LOC
K_G
A
TING
_DIS
ABLE
D
ISP
LA
Y_P
LANE
_
B
_
PS
R
_
CLO
C
K
_
GA
T
ING_D
IS
A
B
LE
SPRITE
_A_PSR_CL
O
CK_GA
T
ING_DIS
A
BLE
SP
RIT
E
_B_PSR_CL
O
CK_GA
T
ING_DIS
A
BLE
SPRITE_C_PSR_CL
O
CK_GA
T
ING_DIS
A
BLE
SP
RIT
E
_D_PSR_CL
O
CK_GA
T
ING_DIS
A
BLE
C
U
RSOR_A_PSR_CL
O
CK_GA
T
ING_DIS
A
BLE
CU
RSOR_B_PSR_CL
O
CK_GA
T
ING_DIS
A
BLE
DIS
P
LA
Y
_
BLENDE
R_A_PSR_C
LOC
K_GA
TING_DIS
ABLE
DIS
PL
A
Y
_
B
LEN
DE
R
_
B
_
PS
R
_
CLO
C
K
_
GA
T
IN
G
_
D
IS
A
B
LE
DISP
LA
Y_G
A
MMA_C
ORRE
CT
ION_A_P
S
R_C
LOC
K_G
A
TING
_DIS
ABLE
DISP
LA
Y
_
G
A
M
M
A_
COR
R
ECTION_B_PSR_CL
O
CK_GA
T
ING_DIS
A
BLE
DIS
P
LA
Y
_
GC
I_PSR_C
LOC
K_GA
TING_DIS
ABLE
AUDFUNIT_PSR_CL
O
CK_GA
T
ING_DIS
A
BLE
AUDBUNIT_PSR_CL
O
CK_GA
T
ING_DIS
A
BLE
CPDUNIT_PSR_C
LOC
K_GA
TING_DIS
ABLE
DDBMUNIT_PSR_CL
O
CK_GA
T
ING_DIS
A
BLE
DPFUNIT_PSR_C
LOC
K_GA
TING_DIS
ABLE
DPIOUNIT_PSR_CL
O
CK_GA
T
ING_DIS
A
BLE
DISPLA
YPOR
T_DPTUNIT_PS
R_CL
OCK_GA
TING_DIS
ABLE
DP
OU
NIT_P
S
R_C
LOC
K_G
A
TING
_DIS
ABLE
HDC
PUNIT_PSR_CL
O
CK_GA
T
ING_DIS
A
BLE
VRDUNIT_PSR_C
LOC
K_GA
TING_DIS
ABLE
V
R
HUNIT_PSR_CL
OCK_GA
TING_DIS
ABLE
DIS
P
LA
Y
_
FU
S
E
_WRAPPER_PSR_CL
OCK_GA
TING_DIS
ABLE
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
LOW_POWER_SINGLE_PIPE_A_LPSSA_CLOCK_GATING_DISABLE:
0 = clock
gating controlled by enabling logic. Pipe A shall be enabled
1 = Disable trunk clock gating on pipe A even when LPSSA is on
30
0b
RW
LOW_POWER_SINGLE_PIPE_B_LPSSA_CLOCK_GATING_DISABLE:
0 = clock
gating controlled by enabling logic. Pipe B shall be enabled
1 = Disable trunk clock gating on pipe B even when LPSSA is on
29:26
0b
RW
RESERVED:
Reserved.
25
0b
RW
DPIO_CLOCK_BUFFER_ENABLE_CLOCK_GATING_DISABLE:
0 = clock gating
controlled by DPIO clock buffer enable
1=Disable clock gating function by DPIO clock buffer enable
24
0b
RW
DISPLAY_PLANE_A_PSR_CLOCK_GATING_DISABLE:
0 = Clock gating controlled
by unit enabling logic
1 = Disable clock gating function
23
0b
RW
DISPLAY_PLANE_B_PSR_CLOCK_GATING_DISABLE:
0 = Clock gating controlled
by unit enabling logic
1 = Disable clock gating function
22
0b
RW
SPRITE_A_PSR_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit
enabling logic
1 = Disable clock gating function
21
0b
RW
SPRITE_B_PSR_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit
enabling logic
1 = Disable clock gating function
20
0b
RW
SPRITE_C_PSR_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit
enabling logic
1 = Disable clock gating function