Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
495
14.10.37 RAMCLK_GATE_D—Offset 6210h
GFX RAM Clock Gating Disable Register ([DevBLC, DevCTG, DevCDV, DevCL]) memory
clock gating (cpdmmreg.v gfxramcg2)
Access Method
Default: 00000000h
1
0b
RW
VRHUNIT_PSR_CLOCK_GATING_DISABLE:
0 = Clock gating controlled by unit
enabling logic
1 = Disable clock gating function
0
0b
RW
DISPLAY_FUSE_WRAPPER_PSR_CLOCK_GATING_DISABLE:
0 = Clock gating
controlled by unit enabling logic
1 = Disable clock gating function
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESE
RVED
PA
NEL_FIT
T
ER_RAM_CL
O
C
K
_GA
T
IN
G_DIS
A
BLE
CU
RS
OR_DA
TA_BUFFER_RAM_CL
O
C
K_GA
T
IN
G
_DIS
ABLE
AU
DM
_UNIT
_
R
A
M_CLOC
K
_
GA
TIN
G
_D
IS
A
B
LE
RESE
RVE
D
_1
DISPLA
Y_DA
TA
_BUFFER1_RAM_CL
O
C
K
_GA
T
IN
G_DIS
A
BLE
HD
CP
_UNIT_RA
M_CLOC
K
_
GA
TIN
G
_D
IS
A
B
LE
DPTUNIT_RAM_CL
O
C
K_GA
T
IN
G
_DIS
ABLE
RESE
RVE
D
_2
RESE
RVE
D
_3
RESE
RVE
D
_4
RESE
RVE
D
_5
RESE
RVE
D
_6
RESE
RVE
D
_7
RESE
RVE
D
_8
RESE
RVE
D
_9
RES
E
RVE
D
_10
RES
E
RVE
D
_11
RES
E
RVE
D
_12
RES
E
RVE
D
_13
RES
E
RVE
D
_14
RES
E
RVE
D
_15
RES
E
RVE
D
_16
RES
E
RVE
D
_17
RES
E
RVE
D
_18
RES
E
RVE
D
_19
RES
E
RVE
D
_20
RES
E
RVE
D
_21
RES
E
RVE
D
_22
RES
E
RVE
D
_23
RES
E
RVE
D
_24
RES
E
RVE
D
_25
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
RESERVED:
[DevCDV]
TVOUT RAM Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
30
0b
RW
PANEL_FITTER_RAM_CLOCK_GATING_DISABLE:
0 = Enable RAM bank clock
gating function (default)
1 = Disable RAM bank clock gating function