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Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
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Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
497
17
0b
RW
RESERVED_8: 
[DevCDV] 
[DevBLC] and [DevCTG] BF Unit RAM Clock Gating Disable: 
[DevCL] URB Clock Gating Disable: 
0 = Enable RAM bank clock gating function (default) 
1 = Disable RAM bank clock gating function
16
0b
RW
RESERVED_9: 
[DevCDV] 
[DevBLC] and [DevCTG] CS Unit RAM Clock Gating Disable: 
[DevCL] L2 Instruction Tag RAM Clock Gating Disable: 
0 = Enable RAM bank clock gating function (default) 
1 = Disable RAM bank clock gating function
15
0b
RW
RESERVED_10: 
[DevBLC, DevCDV] 
[DevCTG] FH Unit RAM Clock Gating Disable: 
[DevCL] Data RAM Clock Gating Disable: 
0 = Enable RAM bank clock gating function (default) 
1 = Disable RAM bank clock gating function
14
0b
RW
RESERVED_11: 
[DevCDV] 
[DevBLC] and [DevCTG] Reserved. 
[DevCL] TAG RAM Clock Gating Disable: 
0 = Enable RAM bank clock gating function (default) 
1 = Disable RAM bank clock gating function
13
0b
RW
RESERVED_12: 
[DevCDV] 
[DevBLC] and [DevCTG] Reserved. 
[DevCL] L2 Instruction Cache Clock Gating Disable: 
0 = Enable RAM bank clock gating function (default) 
1 = Disable RAM bank clock gating function
12
0b
RW
RESERVED_13: 
[DevCDV] 
[DevBLC] and [DevCTG] Reserved. 
[DevCL] MRFRAM Clock Gating Disable: 
0 = Enable RAM bank clock gating function (default) 
1 = Disable RAM bank clock gating function
11
0b
RW
RESERVED_14: 
[DevCDV] 
[DevBLC] and [DevCTG] VFM Unit RAM Clock Gating Disable: 
[DevCL] GRF RAM Clock Gating Disable: 
0 = Enable RAM bank clock gating function (default) 
1 = Disable RAM bank clock gating function
10
0b
RW
RESERVED_15: 
[DevCDV] 
[DevBLC] and [DevCTG] SFM Unit RAM Clock Gating Disable: 
[DevCL] Data Cache CAM Clock Gating Disable: 
0 = Enable RAM bank clock gating function (default) 
1 = Disable RAM bank clock gating function
9
0b
RW
RESERVED_16: 
[DevCDV] 
[DevBLC] and [DevCTG] WIZM Unit RAM Clock Gating Disable: 
[DevCL] Data Cache Gating Disable: 
0 = Enable RAM bank clock gating function (default) 
1 = Disable RAM bank clock gating function
8
0b
RW
RESERVED_17: 
[DevCDV] 
[DevBLC] and [DevCTG] URB Unit RAM Clock Gating Disable: 
[DevCL] Render Cache Latency FIFO Clock Gating Disable: 
0 = Enable RAM bank clock gating function (default) 
1 = Disable RAM bank clock gating function
7
0b
RW
RESERVED_18: 
[DevCDV] 
[DevBLC] and [DevCTG] IC Unit RAM Clock Gating Disable: 
[DevCL] Render PA Tag RAM (Z) Clock Gating Disable: 
0 = Enable RAM bank clock gating function (default) 
1 = Disable RAM bank clock gating function
6
0b
RW
RESERVED_19: 
[DevCDV] 
[DevBLC] and [DevCTG] ISC Unit RAM Clock Gating Disable: 
[DevCL] Render PA Tag RAM (Color) Clock Gating Disable: 
0 = Enable RAM bank clock gating function (default) 
1 = Disable RAM bank clock gating function
Bit 
Range
Default & 
Access
Field Name (ID): Description