Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
498
Datasheet
14.10.38 FW_BLC_SELF—Offset 6500h
Display FIFO Watermark
Access Method
Default: 00000000h
5
0b
RW
RESERVED_20:
[DevCDV]
[DevBLC] and [DevCTG] GA Unit RAM Clock Gating Disable:
[DevCL] Render Cache Write Back FIFO Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
4
0b
RW
RESERVED_21:
[DevCDV]
[DevBLC] and [DevCTG] MS Unit RAM Clock Gating Disable:
[DevCL] Render Cache (Z) Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
3
0b
RW
RESERVED_22:
[DevCDV]
[DevBLC] and [DevCTG] RCBP Unit RAM Clock Gating Disable:
[DevCL] Render Cache (color) Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
2
0b
RW
RESERVED_23:
[DevCDV]
[DevBLC] and [DevCTG] RCC Unit RAM Clock Gating Disable:
[DevCL] L2 Mapping Cache CAM Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
1
0b
RW
RESERVED_24:
[DevCDV]
[DevBLC] and [DevCTG] RCZ Unit RAM Clock Gating Disable:
[DevCL] L2 Mapping Tag RAM Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
0
0b
RW
RESERVED_25:
[DevCDV]
[DevBLC] and [DevCTG] MT Unit RAM Clock Gating Disable:
[DevCL] L2 Mapping Cache Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESE
RVE
D
CS
PW
RD
WNE
N
RES
E
RVE
D
_1