Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
539
14.10.84 MIPIA_CTRL—Offset B104h
MIPI adapter has a control register with options to control width of the dbi bus and the
divide value of the clock that needs to be supplied to the Clocks module so that a 2x
divided clock can be provided to the MIPI D-PHY IP. Self refresh capability is in DCS
commands. The other 3 controls bits (SD, CM and back light control) are now moved to
MIPI IP registers.
Access Method
Default: 00000000h
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
VAL:
0= disable DBI TYPE-C interface (default)
1= enable DBI TYPE-C interface
Driver to make sure that the command and data buffers are cleared before this bit is
changed
30
0b
RW
STATUS:
command and data buffer empty and link completed sending out all serialized
data and IDLE
0 = IDLE
1 = work in progress
29:28
0b
RW
OPTION:
TYPE-C option selection
00 option 1
01 option 2
10 option 3
11 no defined functionality
27:24
0b
RW
FREQ:
Type-C clock frequency ; A counter based onczclk is used to generate the TYPE-C
Clock. So based on the czclk, a frequency close to the specified below will be generated.
Not the exact frequency.
0000 1Mhz (default)
0001 1Mhz
0010 2Mhz
1111 15Mhz
23:9
0b
RW
RESERVED:
Reserved.
8
0b
RW
OVERRIDE:
Use override counter value to derive the TYPE-C clock frequency
7:0
0b
RW
OVERRIDE_COUNTER:
Override counter value to generate the TYPE-C clock
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NAME_BIT
S
ES
CA
PE
_CLO
CK
_DIV
ID
E
R
ST
A
T
US
RGB_FLIP
MI
PI_2X_CL
O
CK_D
IVIDER