Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
552
Datasheet
14.10.101 MIPIC_DSI_FUNC_PRG__REG—Offset B80Ch
mipi C DSI func prg reg
Access Method
Default: 00000001h
16
0b
RW
TXDSI_DATA_TYPE_NOT_RECOGNISED: 
Set to enable the interrupt if the received 
packets data type is not recognised
15
0b
RW
TXCHECKSUM_ERROR: 
Set to enable the interrupt if the computed CRC differs from 
the received CRC value for the received packets
14
0b
RW
TXECC_MULTIBIT_ERROR: 
Set to enable the interrupt if there is no ECC correction 
for the packet or there are more than 2 bit errors in the packet received by Arasan DSI 
host
13
0b
RW
TXECC_SINGLE_BIT_ERROR: 
Set to enable the interrupt if ECC syndrome was 
computed and is corrected for one bit error during the reception of packets by the 
Arasan DSIhost
12
0b
RW
TXFALSE_CONTROL_ERROR: 
Set to enable the interrupt for the control 
error.,observed on the lanes by the Arasan_DSI_host
11
0b
RW
RXDSI_VC_ID_INVALID: 
Set to enable the interrupt for invalid virtual channel ID in 
the acknowledgment packet reports
10
0b
RW
RXDSI_DATA_TYPE_NOT_RECOGNISED: 
Set to enable the interrupt for the un 
recognised data type in the acknowledgment packet reports
9
0b
RW
RXCHECKSUM_ERROR: 
Set to enable the interrupt for the computed CRC differs from 
the received CRC value in the acknowledgment packet reports
8
0b
RW
RXECC_MULTIBIT_ERROR: 
Set to enable the interrupt for no ECC correction for the 
packet or there are more than 2 bit errors reported in the acknowledgment packet
7
0b
RW
RXECC_SINGLE_BIT_ERROR: 
Set to enable the interrupt for ECC syndrome 
computation and one bit error correction for the acknowledgment packet
6
0b
RW
RXFALSE_CONTROL_ERROR: 
Set to enable the interrupt for control error in the 
acknowledgment packet reports
5
0b
RW
RXHS_RECEIVE_TIMEOUT_ERROR: 
Set to enable the interrupt for the high speed 
receive timeout Error in the acknowledgment packet reports
4
0b
RW
RX_LP_TX_SYNC_ERROR: 
Set to enable the interrupt for Low power transmission 
sync error in the acknowledgment packet reports
3
0b
RW
RXESCAPE_MODE_ENTRY_ERROR: 
Set to enable the interrupt for Escape Mode 
Entry command error in the acknowledgment packet reports
2
0b
RW
RXEOTSYNC_ERROR: 
Set to enable the interrupt for End of transmission 
synchronisation Error in the acknowledgement packet reports
1
0b
RW
RXSOTSYNC_ERROR: 
Set to enable the interrupt for start of transmission 
synchronisation error in the acknowledgement packet reports
0
0b
RW
RXSOT_ERROR: 
Set to enable the interrupt for start of transmission error in the 
acknowledgment packet reports
Bit 
Range
Default & 
Access
Field Name (ID): Description
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
GTTMMADR_LSB Type: 
PCI Configuration Register (Size: 32 
bits)
GTTMMADR_LSB Reference: 
[B:0, D:2, F:0] + 10h