Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
580
Datasheet
14.10.137 MIPIC_DATA_ADD—Offset B908h
mipi C data ADD
Access Method
Default: 00000000h
14.10.138 MIPIC_DATA_LEN—Offset B90Ch
mipiC data length
Access Method
Bit
Range
Default &
Access
Field Name (ID): Description
31:5
0b
RW
NAME_BITS:
Reserved
4:3
0b
RW
STATUS:
2'b00: low priority on read requests to G-unit
2'b11 : high priority
2
0b
RW
RGB_FLIP:
1'b0 : RGB data from disp2d is reverted to BGR
1'b1 : RGB data from disp2d is passed as is to MIPI IP
1:0
0b
RW
MIPI_2X_CLOCK_DIVIDER:
Reserved
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DA
TA
_ME
M
_A
DDR
DA
TA
_
M
E
M
_A
DDR_1
DA
TA
_V
A
LID
Bit
Range
Default &
Access
Field Name (ID): Description
31:5
0b
RW
DATA_MEM_ADDR:
When there is updated data for the display panel, S/W programs
this register with the memory address to read from
4:1
0b
RW
DATA_MEM_ADDR_1:
Reserved
0
0b
RW
DATA_VALID:
This bit is set by S/W when the mem_addr is written and is cleared by
H/W when done reading the data from memory
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h