Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

596

Datasheet

Pipe A Data M value 1 

Default: 7E000000h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RE

SE

RVED

PIPE

_A

_SE

C

O

N

D_FIE

LD_

VER

T

IC

AL_SY

N

C_SH

IF

T

31:13

0b

RW

Write as zero.

12:0

0b

RW

This value specifies the vertical 

sync alignment for the start of the interlaced second field expressed in terms of the 

absolute pixel number relative to the horizontal active display start.  

This value will only be used if the PIPEACONF is programmed to an interlaced mode 

using vsync shift. Otherwise a legacy value of floor[htotal / 2] will be used. 

Typically, the interlaced second field vertical sync should start one pixel after the point 

halfway between successive horizontal syncs, so the value of this register should be 

programmed to:  

(horizontal sync start - floor[horizontal total / 2]) (use the actual horizontal sync start 

and horizontal total values and not the minus one values programmed into registers). 

This vertical sync shift only occurs during the interlaced second field. In all other cases 

the vertical sync start position is aligned with horizontal sync start.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h