Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

6

Datasheet

17.14 SATA Secondary Write Command IO Registers................................................... 2012
17.15 SATA Secondary Read Control IO Registers ....................................................... 2014
17.16 SATA Secondary Write Control IO Registers....................................................... 2015
17.17 SATA Lane 0 Electrical Register Address Map ..................................................... 2017
17.18 SATA Lane 0 Electrical Register Address Map ..................................................... 2047
17.19 SATA Lane 1 Electrical Register Address Map ..................................................... 2065
17.20 SATA Lane 1 Electrical Register Address Map ..................................................... 2095

USB Host Controller Interfaces (xHCI, EHCI) ....................................................... 2112
18.1 Signal Descriptions ........................................................................................ 2112
18.2 USB 3.0 xHCI (Extensible Host Controller Interface) ........................................... 2114
18.3 USB 2.0 Enhanced Host Controller Interface (EHCI)............................................ 2115
18.4 References.................................................................................................... 2116
18.5 Register Map................................................................................................. 2117
18.6 USB xHCI PCI Configuration Registers .............................................................. 2120
18.7 USB xHCI Memory Mapped I/O Registers .......................................................... 2163
18.8 USB EHCI PCI Configuration Registers .............................................................. 2345
18.9 USB EHCI Memory Mapped IO Registers ........................................................... 2369
18.10 USB EHCI Electrical Message Bus Registers ....................................................... 2427

USB Device Controller Interfaces (3.0, ULPI) ....................................................... 2443
19.1 USB Device Controller .................................................................................... 2445
19.2 References.................................................................................................... 2446
19.3 Register Map................................................................................................. 2446
19.4 USB 3.0 Device PCI Configuration Registers ...................................................... 2447
19.5 USB 3.0 Device PCI Configuration Registers ...................................................... 2456
19.6 USB 3.0 Device Memory Mapped I/O Registers .................................................. 2461
19.7 USB 3.0 Device Memory Mapped I/O Registers .................................................. 2642

 High Definition Audio ................................................................................ 2662

20.1 Signal Descriptions ........................................................................................ 2663
20.2 Features....................................................................................................... 2664
20.3 References.................................................................................................... 2664
20.4 Register Map................................................................................................. 2665
20.5 HD Audio PCI Configuration Registers ............................................................... 2667
20.6 HD Audio Memory Mapped I/O Registers........................................................... 2698

S) .............................................................. 2798

21.1 Signal Descriptions ........................................................................................ 2798
21.2 Features....................................................................................................... 2799
21.3 Detailed Block Level Description ...................................................................... 2800
21.4 Software Implementation Considerations .......................................................... 2803
21.5 Clocks .......................................................................................................... 2805
21.6 SSP (I

S) ..................................................................................................... 2808

21.7 Programming Model ....................................................................................... 2813
21.8 Register Map................................................................................................. 2818
21.9 Low Power Audio PCI Configuration Registers .................................................... 2819
21.10 pci_mem Address Map.................................................................................... 2827
21.11 Memory Mapped Shim Registers ...................................................................... 2837
21.12 Low Power Audio I

2

S0 Address Map.................................................................. 2864

2

S0 Address Map.................................................................. 2884

2

S0 Address Map.................................................................. 2904

21.15 Low Power Audio DMA0 Memory Mapped IO Registers ........................................ 2924
21.16 Low Power Audio DMA1 Memory Mapped IO Registers ........................................ 3037