Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Physical Interfaces
Intel
®
Atom™ Processor E3800 Product Family
62
Datasheet
2.30
Configurable IO: GPIO Muxing
Not all interfaces may be active at the same time. To provide flexibility, some interfaces
are muxed with configurable IO balls. An interface’s signal is selected by a function
number. See
are muxed with configurable IO balls. An interface’s signal is selected by a function
number. See
details of which balls are muxed, and what functions are available by ball.
Note:
Configurable IO defaults to function 0 at boot. All configurable IO with GPIO’s for
function 0 default to input at boot.
function 0 default to input at boot.
2.31
Reserved Pins
Reserved pins are non functional pins. Unless otherwise specified in this document or
related collateral, reserved pins should not be connected to anything. RSVD_GND pins
must be connect to the common ground plane (VSS), but don’t provide a return path
for currents.
related collateral, reserved pins should not be connected to anything. RSVD_GND pins
must be connect to the common ground plane (VSS), but don’t provide a return path
for currents.
§
Table 31. Straps
Signal Name
Function
Default
Strap Exit
Strap Description
GPIO_S0_SC[056]
Legacy
1b
PMC_CORE_PWROK
de-asserted
Top Swap (A16 Override)
0 = Top address bit is inverted
1 = Top address bit is unchanged
0 = Top address bit is inverted
1 = Top address bit is unchanged
GPIO_S0_SC[063]
Legacy
1b
PMC_CORE_PWROK
de-asserted
BIOS Boot Selection
0 = LPC
1 = SPI
0 = LPC
1 = SPI
GPIO_S0_SC[065]
Legacy
1b
PMC_CORE_PWROK
de-asserted
Security Flash Descriptors
0 = Override
1 = Normal Operation
0 = Override
1 = Normal Operation
DDI0_DDCDATA
Display
0b
PMC_CORE_PWROK
de-asserted
DDI0 Detect
0 = DDI0 not detected
1 = DDI0 detected
0 = DDI0 not detected
1 = DDI0 detected
DDI1_DDCDATA
Display
0b
PMC_CORE_PWROK
de-asserted
DDI1 Detect
0 = DDI1 not detected
1 = DDI1 detected
0 = DDI1 not detected
1 = DDI1 detected