Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

621

Default: 00000000h

Pipe B Horizontal Total Register

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RE

SE

RVED

GC

P_

CO

LO

R

_

IN

DI

C

A

TI

O

N

GC

P_

DEF

A

U

LT

_

PH

A

S

E_

E

N

ABL

E

GCP

_

A

V

_MUTE

31:3

0b

RW

Project: All Format: MBZ 

2

0b

RW

Project: All  

Default Value: 0b  

This bit must be set when in deep color mode. It may optionally be set for 24-bit mode. 

It must be set if the sink attached to Pipe A can receive GCP data.  

Value Name Description Project  

0b Dont Indicate Dont indicate color depth. CD and PP bits in GCP set to zero All  

1b Indicate Indicate color depth using CD bits in GCP. It will be set depending on 

programmed pixel depth in port control register All 

1

0b

RW

Project: All  

Default Value: 0b  

Indicates the video timings meet alignment requirements such that the following 

conditions are met: Htotal is an even number Hactive is an even number Hsync is an 

even number Front and back porches for Hsync are even numbers Vsync always starts 

on an even-numbered pixel within a line in interlaced modes (starting counting with 0)  

Value Name Description Project  

0b Clear Default phase bit in GCP is cleared All  

1b Require Met Default phase bit in GCP is set. All requirements must be met before 

setting this bit All 

0

0b

RW

Project: All  

Default Value: 0b  

Set AV mute bit in GCP  

Value Name Description Project  

0b Clear AV mute bit in GCP is cleared. When this bit transitions to 0, the AV mute clear 

flag is sent in the next GCP packet All  

1b Set AV mute bit in GCP is set. When this bit transitions to 1, the AV mute set flag is 

sent in the next GCP packet All