Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Register Access Methods
Intel
®
Atom™ Processor E3800 Product Family
64
Datasheet
Base address registers are often located in the PCI configuration space and are
programmable by the BIOS/OS. Other base address register types may include fixed
memory registers, fixed IO registers or message bus registers.
programmable by the BIOS/OS. Other base address register types may include fixed
memory registers, fixed IO registers or message bus registers.
3.4
Memory Referenced Register Access
The SoC uses programmable base address registers (BARs) to set a range of physical
address (memory) locations that it will use to decode memory reads and writes from
the CPU to directly access a register. These BARs act as pointers to blocks of actual
memory mapped IO (MMIO) registers. To access a memory referenced register for a
specific base address, start with that base address and add the register’s offset.
Example pseudo code for a read is shown below:
address (memory) locations that it will use to decode memory reads and writes from
the CPU to directly access a register. These BARs act as pointers to blocks of actual
memory mapped IO (MMIO) registers. To access a memory referenced register for a
specific base address, start with that base address and add the register’s offset.
Example pseudo code for a read is shown below:
Register_Snapshot = MEMREAD([Mem_BAR]+Register_Offset)
Base address registers are often located in the PCI configuration space and are
programmable by the BIOS/OS. Other common base address register types include
fixed memory registers and IO registers that point to MMIO register blocks.
programmable by the BIOS/OS. Other common base address register types include
fixed memory registers and IO registers that point to MMIO register blocks.
3.5
PCI Configuration Register Access
Access to PCI configuration space registers is performed through one of two different
configuration access methods (CAMs):
configuration access methods (CAMs):
•
IO indexed - PCI CAM
•
Memory mapped - PCI Enhanced CAM (ECAM)
Each PCI function has a standard PCI header consisting of 256 bytes for the IO access
scheme (CAM), or 4096 bytes for the enhanced memory access method (ECAM).
Invalid read accesses return binary strings of 1s.
scheme (CAM), or 4096 bytes for the enhanced memory access method (ECAM).
Invalid read accesses return binary strings of 1s.
Table 34. Referenced IO Register Access Method Example (HSTS Register)
Type:
I/O Register
(Size: 8bits)
HSTS:
[_IOBAR] + 0h
_IOBAR Type:
PCI Configuration Register (Size: 32 bits)
_IOBAR Reference:
[B:0, D:31, F:3] + 20h
Table 35. Memory Mapped Register Access Method Example (_MBAR Register)
Type:
Memory Mapped I/O Register
(Size: 8bits)
HSTS:
[_MBAR] + 0h
_MBAR Type:
PCI Configuration Register (Size: 32 bits)
_MBAR Reference:
[B:0, D:31, F:3] + 10h
Table 36. PCI Register Access Method Example (VID Register)
Type:
PCI Configuration Register
(Size: 16bits)
VID:
[B:0, D:31, F:3] + 0h