Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

645

Pipe B CRC Color Control Register

Default: 00000000h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ENABLE

_C

OL

OR_CHANNEL_CRC

C

R

C_S

O

U

R

CE

_SE

LEC

T

RE

SE

RVED

EXPECTE

D

_CRC

_V

ALUE

31

0b

RW

After being enabled for the first time, you need to 

wait for two VBLANK events for a valid CRC result. After that, a CRC will be generated 

each frame. 

0 = CRC Calculations are disabled 

1 = CRC Calculations are enabled

30:27

0b

RW

These bits select the source of the data to put into the CRC 

logic. 

0000: Pipe B (Not available when DisplayPort or TV is enabled on this pipe) [DevVLVP] 

0001: sDVOB/HDMIB (30 bit format. Only select when HDMIB is set to pipe B) 

[DevVLVP] 

0010: sDVOC/HDMIC (30 bit format. Only select when HDMIC is set to pipe B) 

[DevVLVP] 

0011: DisplayPort D (40 bit format) [DevCTG] 

0100: TV Encoder outputs (30 bit format)  

0101: TV filter outputs (30 bit format) 

0110: DisplayPort B (40 bit format) [DevCTG, DevCDV, DevVLVP] 

0111: DisplayPort C (40 bit format) [DevCTG, DevCDV, DevVLVP] 

1000: Audio DP (Audio for DisplayPort (pcdclk). Only select when Audio is on 

DisplayPort on Pipe B) [DevVLVP] 

1001: Audio HDMI (Audio for HDMI (dotclock) Only select when Audio is on HDMI on 

Pipe B) 

Others: Reserved 

26:23

0b

RW

Write as zero

22:0

0b

RW

Expected CRC Value for the Color Channel. This is the value 

used to generate the CRC error status and interrupt. Resultant CRC values are 

compared to this register after the completion of a CRC calculation. The status bit is in 

the PIPEBSTAT register.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h