Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

652

Datasheet

Pipe B Panel Self Refresh Control

Default: 00000000h

22:0

0b

RO

This field contains the resultant CRC value 

for the Color Channel at the end of a frame. A status bit can be used as an indication 

that the data is the valid result of a CRC calculation. The result of a CRC on an empty 

frame will be 7FFFFFh.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RE

SERV

ED

ID

ENTICAL_FRAME

_

THRE

SH

OLD

DPLLB_POWER_DO

W

N

_

D

E

LA

Y

DOUBLE

_FRAMES_I

N

_PSR_AC

T

IVE_E

N

T

R

Y

SOURCE_TRAN

S

MIT

T

ER_ST

A

TE

_I

N_PSR_AC

T

IVE

PS

R_AC

TIV

E

_EN

T

R

Y

PSR_SINGLE_FRA

M

E

_UP

D

A

T

E

RE

SE

RVED_1

PS

R

_

MO

DE

PSR_RES

E

T

PS

R_E

N

ABLE

31:24

0b

RW

Reserved.

23:16

0b

RW

: Number of identical frames that display 

controller needs to exceed in order to transition to PSR active state in HW timer mode

15:11

0b

RW

programmable delay from main link powerdown to 

DPLLB powerdown. The delay is in number of cdclk clocks.

10

0b

RW

. If asserted, HW will send two frames 

with same SDP active setting when entry PSR active state. This bit is set if the vertical 

blanking time is less than 330us.

9

0b

RW

. If asserted, HW will keep 

transmitter active during PSR active state and sends only idle symbols. If deasserted, 

HW will turn off transmitter during PSR active state. Display driver will keep this bit 

consistent with Source transmitter state in PSR active bit in DPCD register of the sink.