Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
653
14.11.12 PSRSTATB—Offset 61094h
Pipe B PSR status register
Access Method
Default: 00000000h
8
0b
RW
PSR_ACTIVE_ENTRY:
This bit is only valid in PSR_mode is SW timer mode. If it is
asserted, HW will transition into PSR_active state. If it is deasserted, HW will transition
to PSR_inactive state. SW should not set or clear this bit more than once within one
vblank period.
7
0b
RW
PSR_SINGLE_FRAME_UPDATE:
In PSR SW or HW mode, SW set this bit before
writing registers for a flip. After HW finishes signle frame update, it goes back to PSR
active ? no RFB state. SW driver may send new single frame update request.
Programming note: Reading this bit is updated at the next vblank. Writing this bit to 1
will cause PSR FSM to perform single frame update automatically, no vblank is required.
When single frame update is done, it will automatically go back to PSR active ? no RFB
update. 61094[2:0] = 3b011.
6:5
0b
RW
RESERVED_1:
Reserved.
4:2
0b
RW
PSR_MODE:
b011-111: reserved.
b010: PSR with HW timer. HW timer decides PSR active entry point. PSR active state
exits upon MMIO write registers that may change the frame buffer.
b001: PSR with SW timer. In this mode, SW will keep track of idle frames and buffer
modification in the driver and explicitly specify the entry and exit PSR active state point.
b000: PSR manual (debug) mode. All of PSR state transitions and SDP content is
managed by SW driver. SW is responsible to change SDP content for every frame with
appropriate values to keep PSR panel in synchronized states.
1
0b
RW
PSR_RESET:
If assert all PSR functions are reset back to PSR inactive state. When it
needs to resynchronize source and sync, SW writes 0x2 to DPCD register 600h and to
this bit to get system back to PSR active states. This bit is self clear.
0
0b
RW
PSR_ENABLE:
Panel Self-refresh is enabled. When it is asserted PSR is enabled and
operate in one of the mode that specified by PSR mode.
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DISP
LA
Y_L
O
C
A
L_ST
A
N
DBY_ST
A
T
E
RE
SER
V
ED
REPEA
T
_FRAME_COUNTER
RE
S
E
R
V
E
D
_
1
SD
P_S
E
NT
PSR_
IN_TR
A
NSITION
RE
S
E
R
V
E
D
_
2
PS
R
_
LA
ST_
S
TA
TE
PSR_CURRENT_ST
A
TE