Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
654
Datasheet
14.11.13 PSRCRC1B—Offset 61098h
Pipe B PSR CRC1 register
Access Method
Default: 00000000h
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:30
0b
RO
DISPLAY_LOCAL_STANDBY_STATE: 
:00: D0 idle state, fetch frame buffer from 
system memory  
01: D0i1 not defined in VLVP 
02: D0i2 PSR is active, display controller is trunk gated 
03: D0i3 PSR is active, display controller is power gated
29:24
0b
RO
RESERVED: 
Reserved.
23:16
0b
RO
REPEAT_FRAME_COUNTER: 
: Number of identical frames has been sent by display 
controller. Value is not roll over at 255.
15:9
0b
RO
RESERVED_1: 
Reserved.
8
0b
RO
SDP_SENT: 
it indicates if SDP packet has been sent in current frame.
7
0b
RO
PSR_IN_TRANSITION: 
There is a period that source already committed to PSR active 
but sink did not. SW should not change the source state at this time but wait until this 
status bit is clear. The wait time should in the range of 120-250us in the worst case.
6
0b
RO
RESERVED_2: 
Reserved.
5:3
0b
RO
PSR_LAST_STATE: 
indicate last source state that VLVP PSR state machine were in 
(debug) 
000: PSR_disabled 
001: PSR_inactive 
010: PSR_transition_to_active 
011: PSR_active no RFB update 
100: PSR_active single frame update 
101: PSR_exit
2:0
0b
RO
PSR_CURRENT_STATE: 
indicate current source state that VLVP PSR state machine are 
in 
000: PSR_disabled 
001: PSR_inactive 
010: PSR_transition_to_active 
011: PSR_active no RFB update 
100: PSR_active single frame update 
101: PSR_exit
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
GTTMMADR_LSB Type: 
PCI Configuration Register (Size: 32 
bits)
GTTMMADR_LSB Reference: 
[B:0, D:2, F:0] + 10h