Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

678

Datasheet

28:26

0b

RW

This field selects the number of bits per color sent to a receiver 

device connected to this port. Color format takes place on the Vblank after being 

written. Color format change must be done as a part of mode set since different color 

depths require different pixel clock settings. 

Selecting a pixel color depth higher or lower than the pixel color depth of the frame 

buffer results in dithering the output stream. 

 

000 = 8 bits per color (Default) 

001 = RESERVED for 10 bits per color  

010 = RESERVED for 6 bits per color 

011 = RESERVED 

1xx = RESERVED

25:19

0b

RW

Reserved.

18

0b

RW

Please note that this 

applies to all modes and is instantly updated. 

1 = sDVO/HDMIB Clock output is inverted  

0 = sDVO/HDMIB Clock output is NOT inverted (DEFAULT)

17:16

0b

RW

These bits control the output clock duty cycle to 

enable EMI mitigation on the external HDMI link. 10/90 cycle has been measured to 

have ~13dB EMI improvement over a 50/50 duty cycle. 

00 = (Default) 50/50 duty cycle: Clock output is 0000011111 

01 = 10/90 duty cycle: Clock output is 0111111111 followed by 0000000001 ([DevCL, 

DevCTG, DevCDV] HDMI only) 

10 = 20/80 duty cycle: Clock output is 0011111111 followed by 0000000011 ([DevCL, 

DevCTG, DevCDV] HDMI only) 

11 = Reserved

15

0b

RW

[DevCTG, DevCDV, DevVLVP] 

Port Lane Reversal: This bit reverses the order of the 4 lanes within the port. Port lane 

reversal takes place on the Vblank after being written. It is an OEM configurable feature.  

0 = (Default) Not reversed 

1 = Reversed

14

0b

RW

Reserved.

13

0b

RW

[DevCTG, DevCDV, DevVLVP]  

Clock Output Disable: This bit disables the clock output on the digital output port. For 

8b/10b modes the clock output should be disabled.  

0 = (Default) Clock output enabled  

1 = Clock output disabled ([DevCL] only)

12

0b

RW

[DevCTG, DevCDV, DevVLVP]:  

Scrambling enable: This bit enables scrambling for UDI-related modes using ANSI 8b/

10b or TMDS encoding. It is not used with SDVO encoding. Software must set this bit 

appropriately when enabling the port. Scrambling is reset at the beginning of horizontal 

sync. 

0 Scrambling disabled (Default) 

1 = Scrambling enabled ([DevCL] only)

11:10

0b

RW

These bits select among encoding types. It is set as part of the display 

detection process. Control codes for ANSI 8b/10b and TMDS encoding must be 

programmed using these bits. Please note that ANSI 8b/10b and TMDS encoding can 

only be enabled on one port at a time, as only one HPD pin is available for use between 

ports B and C. 

00 = Reserved 

01 = Reserved 

10 = TMDS encoding ([DevCL, DevCTG, DevCDV, DevVLVP] external link and HDMI 

only) 

See the HDMI specification for control codes. In this mode, the external HPD pin is used 

to generate hotplug. In fixed frequency mode, start of fill and end of fill values for TMDS 

must be programmed using register 6114C.  

11 = Reserved