Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

688

Datasheet

31

0b

RW

When this bit is disabled the MIPI DPI (video mode) is inactive and in it's low power 

state. When it is enable it starts to generate timing for this MIPI port 

0 = The port is disabled and all MIPI DPI interface are disable (timing generator is off) 

1 = The port is enabled

30:27

0b

RW

These four bits act as an encoded count of the number of buffer delays 

to insert on the ckdsi2x clock going to the six flops that are storing the HS TX data and 

clock signals. 

Default is 4'b0000 which is the equivalent of 1 buffer delay. Will need to set these bits to 

a value determined by clock timing team before using the MIPI DSI HS TX feature

26

0b

RW

0 = Front-Back 

mode (default) 

1 = Pixel alternative mode

25

0b

RW

This bit enables or disables (bypassing) 8-6-bit color dithering function. The 

usage of this bit would be on for 18-bpp panels and off for 24-bpp panels. 

0 = disabled 

1 = enabled

24

0b

RW

Reserved.

23

0b

RW

This bit will be used to mux between the flopped (new) and 

unflopped (original) versions of the TX HS clock and data. 

Default 0 = pass through original unflopped version, if set to 1 = pass through the new 

flopped version of these signals. We probably need to enable validation to always set 

these to 1 during startup so we're fully testing this logic as it is the intended way we will 

run A0

22

0b

RW

Reserved.

21:18

0b

RW

These four bits act as an encoded count of the 

number of buffer delays to insert on the ckdsi2x clock going to the six flops that are 

storing the HS TX data and clock signals. 

Default is 4'b0000 which is the equivalent of 1 buffer delay. Will need to set these bits to 

a value determined by clock timing team before using the MIPI DSI HS TX feature

17

0b

RW

This bit reflect the value of the output latch of CLK A lane in DSI AFE 

b1 = current value of output latch is 1 (D-PHY is in LP11 state) 

b0 = current value of output latch is 0 (D-PHY is in LP00 state) 

 

The software driver can read this bit to see if the hold value (LP11 or LP00) to initialize 

from a sleep state (s0i1 or S0i3) correctly

16

0b

RW

0= disable transparent latche inside DSI AFE. Output are driven by 

latch value. 

1= enable transparent latch inside DSI AFE so data are driven by DSI DPHY

15

0b

RW

The fourth bit of four bits act as 

an encoded count of the number of buffer delays to insert on the ckdsi2x clock going to 

the six flops that are storing the HS TX data and clock signals. 

Default is 1'b0 which is the equivalent of 1 buffer delay. Will need to set these bits to a 

value determined by clock timing team before using the MIPI DSI HS TX feature

14:11

0b

RW

These four bits act as an encoded count of the 

number of buffer delays to insert on the ckdsi2x clock going to the six flops that are 

storing the HS TX data and clock signals.[Br] Default is 4'b0000 which is the equivalent 

of 1 buffer delay. Will need to set these bits to a value determined by clock timing team 

before using the MIPI DSI HS TX feature

10:9

0b

RW

Clock input for bandgap voltage sample and hold circuit. 

Final setting will be based silicon characterization. 

00b = 20mhz clock  

01b = 10mhz clock 

10b = 40mhz clock 

11b = reserved