Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

689

mipi A tearing CTR

Default: 00000000h

Display Pipe A Pixel Generator Control 

8

0b

RW

Bandgap chicken bit 

0 = using Penwell band gap circuit  

1 = back to LNC circuit

7:5

0b

RW

The lower 3-bit of four bits act 

as an encoded count of the number of buffer delays to insert on the ckdsi2x clock going 

to the six flops that are storing the HS TX data and clock signals. 

Default is 3'b000 which is the equivalent of 1 buffer delay. Will need to set these bits to 

a value determined by clock timing team before using the MIPI DSI HS TX feature

4

0b

RW

When set, the TE counter will be count down until

3:2

0b

RW

00: No tearing effect required - memory write start as soon as write data is 

available 

01: TE trigger by MIPI DPHY and DSI protocol 

10: TE trigger by GPIO pin 

11: Reserved

1:0

0b

RW

00: All 4 MIPI A lanes are assigned to pipe A.  

All 4 MIPI C lanes are assigned to pipe B.  

01: MIPI dual-link mode with data from pipe A 

10: MIPI dual-link mode with data from pipe B 

11: Reserved 

Programming note: when MIPI dual-link mode is enabled, the port enable bits in both 

MIPI A control register and MIPI C control register shall be enabled.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESE

RVE

D

TE

31:16

0b

RW

Reserved.

15:0

0b

RW

Number of delay clocks from TE trigger to start sending data to DSI controller