Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
694
Datasheet
14.11.40 PIPEA_PP_CONTROL—Offset 61204h
PipeA Panel Power Control Register ([DevCL, DevCTG, DevCDV]) PP Control (dplrreg.v
pnl_pwr_cntl)
Access Method
Default: 00000000h
30
0b
RO
REQUIRE_ASSET_STATUS:
This bit indicates the status of programming of the display
PLL and the selected display port. This a power on cycle will not be allowed unless this
status indicates that the required assets are programmed and ready for use.
0 = All required assets are not properly programmed.
1 = All required assets are ready for the driving of a panel.
The following conditions determine that the assets are ready:
1) Display Pipe PLL Enabled and frequency locked (bit-31 of DPLL Control Register for
the pipe attached to the embedded panel port).
2) Display Pipe Enabled (bit-31 of PIPECONF Pipe Configuration Register. For the pipe
attached to the embedded panel port)
3) Embedded Panel Port is Programmed Enabled
29:28
0b
RO
POWER_SEQUENCE_PROGRESS:
00 = Indicates that the panel is not in a power
sequence
01 = Indicates that the panel is in a power up sequence (may include power cycle delay)
10 = Indicates that the panel is in a power down sequence
11 = Reserved
27
1b
RO
POWER_CYCLE_DELAY_ACTIVE:
Power cycle delays occur after a panel power down
sequence or after a hardware reset. On reset, a power cycle delay will occur using the
default value for the timing.
0 = A power cycle delay is not currently active
1 = A power cycle delay (T4) is currently active
26:4
0b
RO
RESERVED:
Reserved.
3:0
0b
RO
INTERNAL_SEQUENCE_STATE_FOR_TEST_DEBUG:
0000 = Power Off Idle (S0.0)
0001 = Power Off, Wait for cycle delay (S0.1)
0010 = Power Off (S0.2)
0011 = Power Off (S0.3)
0100 = Reserved
0101 = Reserved
0110 = Reserved
0111 = Reserved
1000 = Power On Idle (S1.0)
1001 = Power On, (S1.1)
1010 = Power On, (S1.2)
1011 = Power On, Wait for cycle delay (S1.3)
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reset
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h