Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
695
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WR
IT
E
_
PR
O
T
E
C
T
_
K
E
Y
RE
SE
RVED
ED
P_
PA
NEL
_
V
D
D
_
ENA
B
LE
B
A
CKLIGHT_E
N
ABLE
P
O
WER_DOWN_ON_RE
SET
PO
WE
R
_
ST
A
T
E_T
A
RGE
T
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0b
RW
WRITE_PROTECT_KEY:
ABCD Write protect off
When this field is programmed to anything except the write protect off setting and the
panel is either powered up or in the process of a power up sequence, a set of registers
involved in generation of panel timing or control become write protected. Any write
cycles to those write protected registers, while they will complete as normal, will not
change the value of the register when write protected. When this register field contains
the write protect off key value, write protect will be unconditionally disabled. In
situations where the embedded panel port is unused, the port should remain powered
down and the write protect will be inactive. This field in normal operation should be left
to all zeros and never programmed with the key value. It exists only to allow testing and
workarounds.
List of Write protected registers:
(LVDS and Panel sequencing Registers):
LVDS Digital Display Port Control Address: 61180h 61183h
Pipe A Panel power on sequencing delays - Address: 61208-6120Bh
Pipe A Panel power off sequencing delays Address: 6120Ch 6120Fh
Pipe A Panel power cycle delay and Reference Divisor Address: 61210h 61213
(DPLL registers):
DPLL Control Registers
FPA0 DPLL Divisor Register
FPA1 DPLL Divisor Register 1
FPB0 DPLL Divisor Register
FPB1 DPLL Divisor Register 1
(Display Pipe timing registers except source size)
HTOTAL Horizontal Total Register
HBLANK Horizontal Blank Register
HSYNC_ Horizontal Sync Register
VTOTAL_ Vertical Total Register
VBLANK_ Vertical Blank Register
VSYNC_ Vertical Sync Register
15:4
0b
RW
RESERVED:
Reserved.
3
0b
RW
EDP_PANEL_VDD_ENABLE:
[DevCDV]: Enabling this bit enables the panel vdd if the
embedded panel is DisplayPort, as indicated in bits 31:30 of the panel power on
sequencing. Software must enable this bit for eDP link training. After eDP link training is
done, software must disable it and let the normal panel power sequencing to take
control.
0 = eDP panel Vdd disabled
1 = eDP panel Vdd enabled
[DevCLN] Reserved
2
0b
RW
BACKLIGHT_ENABLE:
[DevCTG, DevCDV]: Enabling this bit enables the panel
backlight if the embedded panel is DisplayPort, as indicated in bits 31:30 of the panel
power on sequencing. Software must enable this bit after training the link, and disable it
when disabling the panel power state target.
0 = Backlight disabled
1 = Backlight enabled
[DevCL] Reserved