Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
698
Datasheet
14.11.43 PIPEA_PP_DIVISOR—Offset 61210h
PipeA Panel Power Cycle Delay and Reference Divisor ([DevCL, DevCTG, DevCDV]) PP
Divisor (dplrreg.v DPLRrefdiv_pp_cd)
Access Method
Default: 00270F04h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
SE
RVED
POWER
_
D
O
WN_DELA
Y
RESE
RVED
_1
PO
W
E
R_BAC
K
LIG
H
T
_
OFF_T
O
_P
OWER
_D
OWN_DELA
Y
Bit
Range
Default &
Access
Field Name (ID): Description
31:29
0b
RW
RESERVED:
Reserved.
28:16
0b
RW
POWER_DOWN_DELAY:
Programmable value of panel power sequencing delay during
power up. This provides the time delay for the T3 (T5 for DisplayPort) time sequence.
The time unit used is the 100us timer.
15:13
0b
RW
RESERVED_1:
Reserved.
12:0
0b
RW
POWER_BACKLIGHT_OFF_TO_POWER_DOWN_DELAY:
Programmable value of
panel power sequencing delay during power down. This provides the time delay for the
Tx (T4 for DisplayPort) time sequence. The time unit used is the 100us timer.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h