Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
703
14.11.48 PIPEA_BLC_PWM_CLT2—Offset 61250h
PipeA Backlight PWM Control Register 2
Access Method
Default: 00000000h
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:0
0b
RW
RESERVED: 
Reserved.
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
GTTMMADR_LSB Type: 
PCI Configuration Register (Size: 32 
bits)
GTTMMADR_LSB Reference: 
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PWM_E
N
A
B
LE
RES
E
RVE
D
__MBZ
RES
E
RVE
D
_
BACKLIGH
T_POLARIT
Y
RES
E
RVE
D
PH
ASE
_IN_INTE
RRUPT_S
TA
TUS
PH
ASE
_IN_E
N
A
B
LE
PH
AS
E_IN_I
NTE
RRUPT_E
NA
BL
E
PHASE_IN_TIME_BASE
PHAS
E
_
IN_CO
U
NT
PH
ASE
_
IN_
INC
R
EM
ENT
Bit 
Range
Default & 
Access
Field Name (ID): Description
31
0b
RW
PWM_ENABLE: 
This bit enables the PWM counter logic 
0 = PWM disabled (drives 0 always) 
1 = PWM enabled
30
0b
RW
RESERVED__MBZ: 
Reserved.
29
0b
RW
RESERVED_: 
Reserved.
28
0b
RW
BACKLIGHT_POLARITY: 
This field controls the polarity of the PWM signal. 
0 = Active High 
1 = Active Low
27
0b
RW
RESERVED: 
MBZ
26
0b
RW/1C
PHASE_IN_INTERRUPT_STATUS: 
This bit will be set by hardware when a Phase-In 
interrupt has occurred. Software will clear this bit by writing a 1 , which will reset the 
interrupt generation. 
[DevCL-A,B] Reserved 
AccessType: One to Clear
25
0b
RW
PHASE_IN_ENABLE: 
Setting this bit enables a PWM phase in based on the 
programming of the Phase In registers below. This bit clears itself when the phase in is 
completed.