Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

705

PipeA Image Enhancement Histogram Control Register

Default: 00000000h

31:16

0b

RW

This field determines the number of time 

base events in total for a complete cycle of modulated backlight control. This field is 

normally set once during initialization based on the frequency of the clock that is being 

used and the desired PWM frequency. This value represents the period of the PWM 

stream in display core clocks ([DevCTG] 100MHz HRAW clocks) multiplied by 128 or 

25MHz S0IX clocks multipled by 16.

15:0

0b

RW

This field determines the number of time base events for 

the active portion of the PWM backlight control. This should never be larger than the 

frequency field. A value of zero will turn the backlight off. A value equal to the backlight 

modulation frequency field will be full on. This field gets updated when it is desired to 

change the intensity of the backlight, it will take affect at the end of the current PWM 

cycle. This value represents the active time of the PWM stream in display core clock 

([DevCTG] HRAW clock) periods multiplied by 128 or 25MHz S0IX clocks multipled by 

16.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IMAG

E_ENH

A

NC

EMENT_H

IST

OG

RA

M

_

E

N

ABLED

IM

AG

E_

E

N

H

A

NC

EM

ENT

_

M

O

D

IF

ICA

T

ION

_

TAB

LE

_

E

NA

B

LE

D

R

E

S

E

R

V

ED

_MB

Z

_IMA

GE

_E

NHA

N

CE

ME

NT

_PIPE

_

ASSIG

N

MEN

T

RESE

RVED

HI

S

TOG

RAM

_

M

O

DE

_SELE

C

T

SYNC

_T

O_P

H

AS

E_IN_CO

U

NT

RES

E

RVE

D

_1

ENHA

NCE

M

ENT_MODE

SYNC_T

O_PHASE_IN

BIN_REGIST

ER_FUN

CTION_SELEC

T

RES

E

RVE

D

_2

BIN_

REGISTER_

IND

EX_READ_ONL

Y