Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

711

31:16

0b

RW

ABCD Write protect off 

When this field is programmed to anything except the write protect off setting and the 

panel is either powered up or in the process of a power up sequence, a set of registers 

involved in generation of panel timing or control become write protected. Any write 

cycles to those write protected registers, while they will complete as normal, will not 

change the value of the register when write protected. When this register field contains 

the write protect off key value, write protect will be unconditionally disabled. In 

situations where the embedded panel port is unused, the port should remain powered 

down and the write protect will be inactive. This field in normal operation should be left 

to all zeros and never programmed with the key value. It exists only to allow testing and 

workarounds. 

List of Write protected registers: 

(Panel sequencing Registers): 

Pipe B Panel power on sequencing delays - Address: 61308-6130Bh 

Pipe B Panel power off sequencing delays Address: 6130Ch 6130Fh 

Pipe B Panel power cycle delay and Reference Divisor Address: 61310h 61313 

(DPLL registers): 

DPLL Control Registers  

FPA0 DPLL Divisor Register  

FPA1 DPLL Divisor Register 1  

FPB0 DPLL Divisor Register  

FPB1 DPLL Divisor Register 1  

(Display Pipe timing registers except source size) 

HTOTAL Horizontal Total Register  

HBLANK Horizontal Blank Register  

HSYNC_ Horizontal Sync Register  

VTOTAL_ Vertical Total Register  

VBLANK_ Vertical Blank Register  

VSYNC_ Vertical Sync Register

15:4

0b

RW

Reserved.

3

0b

RW

[DevCDV]: Enabling this bit enables the panel vdd if the 

embedded panel is DisplayPort, as indicated in bits 31:30 of the panel power on 

sequencing. Software must enable this bit for eDP link training. After eDP link training is 

done, software must disable it and let the normal panel power sequencing to take 

control. 

0 = eDP panel Vdd disabled 

1 = eDP panel Vdd enabled 

[DevCLN] Reserved

2

0b

RW

[DevCTG, DevCDV]: Enabling this bit enables the panel 

backlight if the embedded panel is DisplayPort, as indicated in bits 31:30 of the panel 

power on sequencing. Software must enable this bit after training the link, and disable it 

when disabling the panel power state target. 

0 = Backlight disabled 

1 = Backlight enabled 

[DevCL] Reserved

1

0b

RW

Enabling this bit causes the panel to power down when a 

reset warning comes to the GMCH from the ICH. When system reset is initiated, the 

embedded panel port automatically begins the panel power down sequence. If the panel 

is not on during a reset event, this bit is ignored. 

0 = Do not run panel power down sequence when reset is detected 

1 = Run panel power down sequence when system is reset

0

0b

RW

Writing this bit can occur any time, it will only be used at 

the completion of any current power cycle. 

0 = The panel power state target is off, if the panel is either on or in a power on 

sequence, a power off sequence is started as soon as the panel reaches the power on 

state. This may include a power cycle delay. If the panel is currently off, there is no 

change of the power state or sequencing done. 

1= The panel power state target is on, if the panel is in either the off state or a power 

off sequence, if all pre-conditions are met, a power on sequence is started as soon as 

the panel reaches the power off state. This may include a power cycle delay. If the panel 

is currently off, there is no change of the power state or sequencing done. While the 

panel is on or in a power on sequence, the register write lock will be enabled.