Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

714

Datasheet

Default: 00270F04h

PipeB Backlight PWM Control Register 2

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0

RE

FERE

N

C

E

_

D

IVIDER

RE

SE

RVED

PO

WE

R

_

CY

CLE_D

E

LA

Y

31:8

000000000

010011100

001111b

RW

This field provides the value of the divider used for the 

creation of the panel timer reference clock. The output of the divider is used as the 

fastest of the three time bases (100us) for all other timers. The other time bases are 

divided from this frequency. The value of zero should not be used. When it is desired to 

divide by N, the actual value to be programmed is (N/2)-1. The value should be 

(100*RefinMHz/2)-1. The default value assumes the default value for the display core 

clock that is for [DevCL and DevCTG] a 200MHz reference value. The following are 

examples for other memory speeds. 

Display Core Frequency Value of Field 

233MHz 2D81h 

200MHz 270Fh 

133MHz 19F9h

7:5

0b

RW

Reserved.

4:0

00100b

RW

Programmable value of time panel must remain in a powered 

down state after powering down. For devices coming out of reset, the default values will 

define how much time must pass before a power on sequence can be started. This field 

uses the .1 S time base unit from the divider. If the panel power on sequence is 

attempted during this delay, the power on sequence will commence once the power 

cycle delay is complete. Writing a value of 0 selects no delay or is used to abort the 

delay if it is active. 

During the initial power up reset, a D3 cold power cycle, or a user instigated system 

reset, the timer will be set to the default value and the count down will begin after the 

de-assertion of reset. Writing this field to a zero while the count is active will abort this 

portion of the sequence. This corresponds to the T4 of the SPWG specification. Note: 

Even if the panel is not enabled, the T4 count happens after reset. 

This register needs to be programmed to a +1 value. For instance for meeting the SPWG 

specification of 400mS, program 5 to achieve at least 400mS delay prior to powerup.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h