Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
716
Datasheet
14.11.59 PIPEB_BLC_PWM_CTL—Offset 61354h
PipeB Backlight PWM Control Register
Access Method
Default: 00000000h
14.11.60 PIPEB_BLM_HIST_CTL—Offset 61360h
PipeB Image Enhancement Histogram Control Register
Access Method
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
B
A
CKLIGHT_MOD
U
LA
TION_FRE
QUENCY
BA
CK
LIGH
T_DUTY
_CY
C
LE
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0b
RW
BACKLIGHT_MODULATION_FREQUENCY:
This field determines the number of time
base events in total for a complete cycle of modulated backlight control. This field is
normally set once during initialization based on the frequency of the clock that is being
used and the desired PWM frequency. This value represents the period of the PWM
stream in display core clocks ([DevCTG] HRAW clocks) multiplied by 128 or 25MHz S0IX
clocks multipled by 16.
15:0
0b
RW
BACKLIGHT_DUTY_CYCLE:
This field determines the number of time base events for
the active portion of the PWM backlight control. This should never be larger than the
frequency field. A value of zero will turn the backlight off. A value equal to the backlight
modulation frequency field will be full on. This field gets updated when it is desired to
change the intensity of the backlight, it will take affect at the end of the current PWM
cycle. This value represents the active time of the PWM stream in display core clock
([DevCTG] HRAW clock) periods multiplied by 128 or 25MHz S0IX clocks multipled by
16.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h