Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
720
Datasheet
14.11.63 MIPIC_PORT_CTRL—Offset 61700h
mipi C port ctrl
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HIST
OGRAM_INTE
RRU
PT_E
NABLE
HIS
TOG
RAM_EV
ENT_ST
A
T
US_REA
D_ONL
Y
GUA
R
DBAND_INTE
RRUPT
_DELA
Y
TH
RESH
OLD_GUA
R
DBAND
Bit 
Range
Default & 
Access
Field Name (ID): Description
31
0b
RW
HISTOGRAM_INTERRUPT_ENABLE: 
0 = Disabled 
1 = Enabled. This generates a histogram interrupt once a Histogram event occurs.
30
0b
RO
HISTOGRAM_EVENT_STATUS_READ_ONLY: 
When a Histogram event has occured, 
this will get set by the hardware. For any more Histogram events to occur, the software 
needs to clear this bit by writing a '1'. The default state for this bit is '0'. 
0 = Histogram event has not occurred. 
1 = Histogram event has occurred. 
AccessType: Read Only
29:22
0b
RW
GUARDBAND_INTERRUPT_DELAY: 
An interrupt is generated after this many 
consecutive frames of the guardband threshold being surpassed. This value is double 
buffered on start of vblank. A value of 0 is invalid.
21:0
0b
RW
THRESHOLD_GUARDBAND: 
This value is used to determine the guardband for the 
threshold interrupt generation. This single value is used for all the segments. This value 
is double buffered on start of vblank
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
GTTMMADR_LSB Type: 
PCI Configuration Register (Size: 32 
bits)
GTTMMADR_LSB Reference: 
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EN
RESE
RVE
D
DIT
H
ER
RES
E
RVE
D
_1
RES
E
RVE
D
_2
RES
E
RVE
D
_3
RES
E
RVE
D
_4
RES
E
RVE
D
_5
RES
E
RVE
D
_6
RES
E
RVE
D
_7
DEL
A
Y
EFFE
CT
RES
E
RVE
D
_8