Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
721
14.11.64 MIPIC_TEARING_CTR—Offset 61704h
mipi C tearing ctr
Access Method
Default: 00000000h
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
EN:
When this bit is disabled the MIPI DPI (video mode) is inactive and in it's low power
state. When it is enable it starts to generate timing for this MIPI port
0 = The port is disabled and all MIPI DPI interface are disable (timing generator is off)
1 = The port is enabled
30:26
0b
RW
RESERVED:
Reserved.
25
0b
RW
DITHER:
This bit enables or disables (bypassing) 8-6-bit color dithering function. The
usage of this bit would be on for 18-bpp panels and off for 24-bpp panels.
0 = disabled
1 = enabled
24:22
0b
RW
RESERVED_1:
Reserved.
21
0b
RW
RESERVED_2:
Reserved.
20
0b
RW
RESERVED_3:
Reserved.
19
0b
RW
RESERVED_4:
Reserved.
18:16
0b
RW
RESERVED_5:
Reserved.
15
0b
RW
RESERVED_6:
Reserved.
14:5
0b
RW
RESERVED_7:
Reserved.
4
0b
RW
DELAY:
When set, the TE counter will be count down until
3:2
0b
RW
EFFECT:
00: No tearing effect required - memory write start as soon as write data is
available
01: TE trigger by MIPI DPHY and DSI protocol
10: TE trigger by GPIO pin
11: Reserved
1:0
0b
RW
RESERVED_8:
Reserved.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h