Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
742
Datasheet
14.11.82 AUD_CONFIG_B—Offset 62100h
Audio Configuration Pipe B 
Access Method
Default: 00000000h
29
0b
RW
CONV_A_CDCLK_DOTCLK_FIFO_UNDERRUN: 
Project: All  
This bit indicates an underrun in the FIFO inside the clock crossing logic between CDCLK 
and DOTCLK. Clearing this status bit is accomplished by writing a 1 to this bit through 
MMIO. 
28
0b
RW
CONV_A_CDCLK_DOTCLK_FIFO_OVERRUN: 
Project: All  
This bit indicates an overrun in the FIFO inside the clock crossing logic between CDCLK 
and DOTCLK. Clearing this status bit is accomplished by writing a 1 to this bit through 
MMIO. 
27:26
0b
RW
RESERVED: 
Project: All Format: 
25
0b
RW
BCLK_CDCLK_FIFO_OVERRUN: 
Project: All  
This bit indicates an overrun in the FIFO inside the clock crossing logic between BCLK 
and CDCLK. Clearing this status bit is accomplished by writing a 1 to this bit through 
MMIO. 
24
0b
RW
FUNCTION_RESET: 
Project: All Security: Debug  
This bit indicates that an audio function reset occurred through the reset signal on the 
HD audio bus. Clearing this status bit is accomplished by writing a 1 to this bit through 
MMIO. 
23:0
0b
RW
RESERVED_1: 
Project: All Format: 
Bit 
Range
Default & 
Access
Field Name (ID): Description
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
GTTMMADR_LSB Type: 
PCI Configuration Register (Size: 32 
bits)
GTTMMADR_LSB Reference: 
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
SERV
ED
N_V
A
LU
E_INDEX
N_PROGRAMMING
_ENABLE_
T
E
ST
M
O
DE
UP
PER_
N_V
A
LUE_
TES
T
M
O
DE
PIXEL_C
LO
C
K_H
D
M
I
LO
W
E
R
_
N
_
V
A
LU
E_
TE
S
T
M
O
D
E
DIS
A
BLE
_
N
C
T
S
RE
S
E
R
V
E
D
_
1