Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

743

Audio MISC Control for Pipe B 

Default: 00000044h

31:30

0b

RW

Project: All Format: 

29

0b

RW

Project: All  

Default Value: 0b  

Value Name Description Project  

0b HDMI N value read on bits 27:20 and 15:4 reflects HDMI N value. Bits 27:20 and 

15:4 are is programmable to any N value - default h7FA6. All  

1b DP N value read on bits 27:20 and 15:4 reflects DP N value. Set this bit to 1 before 

programming N value register. When this is set to 1, 27:20 and 15:4 will reflect the 

current N value default h8000. All 

28

0b

RW

Project: All Security: Test  

See Pipe A description. 

27:20

0b

RW

Project: All Security: Test  

See Pipe A description 

19:16

0b

RW

Project: All  

Default Value: 0b  

See Pipe A description.  

Value Name Description Project  

0000b 25.2 / 1.001 MHz 25.2 / 1.001 MHz All  

0001b 25.2 MHz 25.2 MHz Program this value for pixel clocks not listed in this field All  

0010b 27 MHz 27 MHz All  

0011b 27 * 1.001 MHz 27 * 1.001 MHz All  

0100b 54 MHz 54 MHz All  

0101b 54 * 1.001 MHz 54 * 1.001 MHz All  

0110b 74.25 / 1.001 MHz 74.25 / 1.001 MHz All  

0111b 74.25 MHz 74.25 MHz All  

1000b 148.5 / 1.001 MHz 148.5 / 1.001 MHz All  

1001b 148.5 MHz 148.5 MHz All  

others Reserved Reserved All 

15:4

0b

RW

Project: All Security: Test  

See Pipe A description 

3

0b

RW

Project: All  

See Pipe A description 

2:0

0b

RW

Project: All Format: 

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h