Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
777
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
DISP
LA
Y
P
O
R
T_B_E
N
ABLE
PI
PE
_
S
EL
E
C
T
LINK_TRAIN
ING_P
A
TT
ER
N
_
ENABLE
RE
SE
RVED
RESE
RVED
_1
POR
T
_WI
D
T
H
_SE
LECTION
ENH
A
N
C
ED_FRAMING
_ENABLE
RESE
RVED
_2
RESE
RVED
_3
RESE
RVED
_4
AS
R
_
ENA
B
LE
SC
RAMBLING
_DIS
ABLE
AUD
IO
_
OU
TP
UT
_ENA
B
LE
H
D
CP_P
OR
T
_
SE
LE
C
T
SY
NC_P
OL
ARITY
DIGIT
A
L_DIS
P
LA
Y
_
B_DET
E
C
T
ED
RESE
RVED
_5
DIS
A
BLE
_
FRAMEST
A
R
T
_
S
TA
LL
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
DISPLAYPORT_B_ENABLE:
Disabling this port will put it in its lowest power state.
Port enable takes place on the Vblank after being written.
1 = Enable. This bit enables the Display Port B interface.
0 = Disable and tristates the Display Port B interface.
30
0b
RW
PIPE_SELECT:
This bit determines from which display pipe the source data will
originate. Pipe selection takes place on the Vblank after being written
0 = Pipe A
1 = Pipe B
29:28
0b
RW
LINK_TRAINING_PATTERN_ENABLE:
These bits are used for link initialization as
defined in the DisplayPort specification. Please note that the link must first be
configured prior to sending training patterns.
00 Pattern 1 enabled: Repetition of D10.2 characters Default.
01 Pattern 2 enabled: Repetition of K28.5, D11.6, K28.5, D11.6, D10.2, D10.2, D10.2,
D10.2, D10.2, D10.2. Please note that the entire pattern must complete before another
pattern is sent. Scrambling initialization and disparity init commence at the end of the
last iteration of pattern 2.
10 Idle Pattern enabled: Transmit BS followed by VB-ID with NoVideoStream_flag set to
1, five times
11 Link not in training: Send normal pixels
27:25
0b
RW
RESERVED:
[DevCDV]:
Voltage swing level set: [DevCTG]: These bits are used for setting the voltage swing for
pattern 1, defined as Vdiff_pp in the DisplayPort specification. They mirror registers in
the PCI express configuration (At CDV moved to register at the DPIO)
000 0.4V (DEFAULT)
001 0.6V
010 0.8V
011 1.2V RESERVED
1xx RESERVED
24:22
0b
RW
RESERVED_1:
[DevCDV]:
Pre-emphasis level set [DevCTG]: These bits are used for setting link pre-emphasis for
pattern 2, as defined in the DisplayPort specification. They mirror registers in the PCI
express configuration. At CDV this field move to register in the DPIO.
000 no pre-emphasis (default)
001 3.5dB pre-emphasis (1.5x)
010 6dB pre-emphasis (2x)
011 9.5dB pre-emphasis (3x) RESERVED
1xx RESERVED