Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

778

Datasheet

21:19

0b

RW

This bit selects the number of lanes to be enabled on the 

DisplayPort link. Port width selection takes place on the Vblank after being written. Port 

width change must be done as a part of mode set. 

000 = x1 Mode (Default) 

001 = x2 Mode.  

010 = RESERVED 

011 = x4 Mode.  

1xx = RESERVED 

18

0b

RW

This bit selects enhanced framing. It must be set 

when HDCP will be used invoked. 

0 (Default) Enhanced framing disabled 

1 Enhanced framing enabled. 

Locked once port is enabled. Updates when the port is disabled then re-enabled

17:16

0b

RW

MBZ

15

0b

RW

[DevCDV]:  

Port reversal [DevCTG]: 

Locked once port is enabled. Updates when the port is disabled then re-enabled

14:9

0b

RW

MBZ

8

0b

RW

[DevVLV2]: this bit enables the Alternate Scrammbler Reset capability 

for eDP port to use alternate scrambler reset value of FFFEh 

1 - ASR enable  

0 ASR disable

7

0b

RW

[DevCTG, B-step only, DevCDV]: This bit disables 

scrambling for this port.  

0 = Scrambling enabled (Default) 

1 = Scrambling disabled, no SR after initialization at loop 2 of training

6

0b

RW

This bit enables audio on this output port. It may be 

enabled or disabled only when the link training is complete and set to Normal  

0 = Audio output disabled 

1 = Audio output enabled

5

0b

RW

This bit directs HDCP to this port. When enabled, the 

information sent on this port will be encrypted using HDCP. Please note that this bit does 

not enable encryption on its own, but must be used in conjunction with HDCP registers. 

0 = (Default) No HDCP encryption on this port 

1 = Enable HDCP on this port 

4:3

11b

RW

Indicates the polarity of Hsync and Vsync.  

Please note that in native VGA modes, these bits have no effect. In native VGA modes, 

sync polarity is determined by VRshr3c2d76b[7:6], the VGA polarity bits in VGA control. 

00 = VS and HS are active low (inverted) 

01 = VS is active low (inverted), HS is active high 

10 = VS is active high, HS is active low (inverted) 

11 = (Default) VS and HS are active high

2

0b

RO

Read-only bit indicating whether a digital display 

was detected during initialization. It signifies the level of the GMBUS port 4 (port B) data 

line at boot. 

0 = digital display not detected during initialization (Default) 

1 = digital display detected during initialization  

AccessType: Read Only

1

0b

RW

MBZ

0

0b

RW

This bit, when set, will disable the framestart 

window to stall DP AV mixer from sending audio samples before framestart. This applies 

to BOTH pipes.  

0 = Enable framestart window to stall audio samples. (default)  

1 = Disable framestart window to stall audio samples.