Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
787
14.11.125 DP_C—Offset 64200h
Display Port C Control Register [DevCTG, DevCDV,DevVLV] Display Port C control
(dprrega_b0.v ql_displayc1)
Access Method
Default: 00000018h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
D
ISP
LA
YP
OR
T_C_E
N
ABLE
PI
PE
_
S
EL
E
C
T
LINK_TRAIN
ING_P
A
TT
ERN
_
ENABLE
RE
S
E
R
V
E
D
RESE
RVE
D
_1
POR
T
_WID
TH_SELECTION
ENH
A
NC
ED_FRAMING
_ENABLE
RESE
RVE
D
_2
RESE
RVE
D
_3
RESE
RVE
D
_4
AS
R
_
ENA
B
LE
SC
RA
MBL
ING
_DIS
ABLE
AUD
IO
_
OU
TP
UT
_ENA
B
LE
H
D
CP_P
OR
T
_
SE
LE
C
T
SY
NC_
POL
A
R
IT
Y
D
IG
IT
A
L_DISPLA
Y_C_DET
E
CTED
RESE
RVE
D
_5
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
DISPLAYPORT_C_ENABLE:
Disabling this port will put it in its lowest power state.
Port enable takes place on the Vblank after being written. Both this bit and bit 6 of this
register must be enabled to send audio over this port.
1 = Enable. This bit enables the Display Port C interface.
0 = Disable and tristates the Display Port C interface.
30
0b
RW
PIPE_SELECT:
This bit determines from which display pipe the source data will
originate. Pipe selection takes place on the Vblank after being written
0 = Pipe A
1 = Pipe B
29:28
0b
RW
LINK_TRAINING_PATTERN_ENABLE:
These bits are used for link initialization as
defined in the DisplayPort specification. Please note that the link must first be
configured prior to sending training patterns.
00 Pattern 1 enabled: Repetition of D10.2 characters Default.
01 Pattern 2 enabled: Repetition of K28.5, D11.6, K28.5, D11.6, D10.2, D10.2, D10.2,
D10.2, D10.2, D10.2. Please note that the entire pattern must complete before another
pattern is sent. Scrambling initialization and disparity init commence at the end of the
last iteration of pattern 2.
10 Idle Pattern enabled: Transmit BS followed by VB-ID with NoVideoStream_flag set to
1, five times
11 Link not in training: Send normal pixels
27:25
0b
RW
RESERVED:
[DevCDV]:
Voltage swing level set [DevCTG]: These bits are used for setting the voltage swing for
pattern 1, defined as Vdiff_pp in the DisplayPort specification. They mirror registers in
the PCI express configuration.
000 0.4V (DEFAULT)
001 0.6V
010 0.8V
011 1.2V RESERVED
1xx RESERVED