Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

790

Datasheet

Display Port C AUX Data Register 1 [DevCTG, DevCDV] AuxC Data1 (dprrega_b0.v 

auxc_dpr_data1, ql_auxc_d1)

27:26

0b

RW

00: 400us (default) 

01: 600us 

10: 800us 

11: 1600us 

The time count depends on the 2X bit clock divider (bits 10:0) being programmed for 

2MHz.

25

0b

RW/1C

A sticky bit that indicates that the data received was corrupted, not 

in multiples of a full byte, or more than 20 bytes. SW must write a 1 to this bit to clear 

the event.  

AccessType: One to Clear

24:20

0b

RW

This field is used to indicate the total number bytes to transmit 

(including the header). It also indicates the number of bytes received in a transaction 

(including the header). This field is valid only only when the done bit is set and timeout 

or receive error has not occurred. Sync/Stop are not part of the message or the 

message size. 

Reads of this field will give the response message size.  

The read value will not be valid while Busy bit 31 is asserted. 

Message sizes of 0 or )20 are not allowed.

19:16

0101b

RW

Used to determine the precharge time for the Aux Channel 

drivers.  

The value is the number of microseconds times 2.  

This depends on the 2X bit clock divider (bits 10:0) being programmed for 2MHz. 

Default is 5 decimal which gives 10us of precharge. 

Example: 

For 12us precharge, program 6 (12us/2us).

15

0b

RW

This bit selects whether some of the data to be written 

over Display Port AUX comes from the Aksv buffer for HDCP authentication, or all from 

the AUX Data registers.  

Set this bit before initiating a transaction to write Aksv to the Display Port sink. All AUX 

protocol must be followed and Message Size set to 9 bytes. The first DWord transmitted 

will be from the AUX Data Register 1 for the header, then the DP_AUX_CH_AKSV_HI, 

then the last byte from DP_AUX_CH_AKSV_LO. The sink response is read back as usual 

from the AUX Data registers. 

More than one AUX channel can select to use the Aksv buffer simultaneously. 

0 (Default) Use AUX Data registers for regular data transmission 

1 Use Aksv Buffer for part of the data transmission.

14

0b

RW

1 = Manchester code rising edge mid-clk 

signifies one (test mode) 

0 = Manchester code rising edge mid-clk signifies zero (default)

13

0b

RW

1 = Only recover clock during sync 

pattern (test mode) 

0 = Recover clock during sync pattern and data phase (default)

12

0b

RW

1 = Disable serial input de-glitch logic (test 

mode) 

0 = Enable serial input de-glitch logic (default)

11

0b

RW

1 = Precharge time is doubled  

0 = Precharge time is as programmed

10:0

0b

RW

Used to determine the 2X bit clock the Aux Channel logic 

runs on. 

This value divides the input clock frequency down to 2X bit clock rate. The 2X bit clock 

rate is ideally 2MHz (0.5us). 

[DevCTG-A] the input clock is cdclk. 

[DevCTG-B] the input clock is hrawclk. 

Example: 

For 300MHz input clock and desired 2MHz 2X bit clock, program 150 (300MHz/2MHz).