Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Integrated Clock
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
81
Table 46. SoC Clock Inputs 
Clock Domain
Signal Name
Frequency
Usage/Description
Main ICLK_OSCIN 
ICLK_OSCOUT
25 MHz
Reference crystal for the iCLK PLL
RTC
ILB_RTC_X1
ILB_RTC_X2
32.768 kHz
RTC crystal I/O for RTC block
MIPI CSI
MCSI1_CLKP/N
MCSI2_CLKP/N
MCSI3_CLKP/N
80-500 MHz 
Clocks for cameras
LPC
ILB_LPC_CLK[1]
33 MHz
Can be configured as an input to 
compensate for board routing delays 
through Soft Strap.
USB PHY
USB_ULPI_CLK
60 MHz
Interface clock from ULPI PHY.
Table 47. SoC Clock Outputs (Sheet 1 of 2)
Clock Domain
Signal Name
Frequency
Usage/Description
Memory
DRAM0_CKP/N[2,0]
DRAM1_CKP/N[2,0]
533/667 MHz
Drives the Memory ranks 0-1. Data 
rate (MT/s) is 2x the clock rate.
Note: The frequency is fused in each 
SoC. It is not possible to support both 
frequencies on one SoC.
eMMC
MMC1_CLK
MMC1_45_CLK
25-50 MHz
25-200 MHz
Clock for eMMC 4.41 devices
Clock for eMMC 4.51 devices
Actual clock can run as low as 400 
kHz during initialization.
SDIO
SD2_CLK
25-50 MHz
Clock for SDIO devices
SD Card
SD3_CLK
25-50 MHz
Clock for SD card devices
SPI
PCU_SPI_CLK
20 MHz,  
33 MHz,  
50 MHz
Clock for SPI flash
PMIC/COMMS
PMC_SUSCLK[3:0]
32.768 kHz
Pass through clock from RTC oscillator
LPC
ILB_LPC_CLK[0:1]
33 MHz 
Provided to devices requiring LPC 
clock
HDA
HDA_CLK
24 MHz
Serial clock for external HDA codec 
device
PCI Express
PCIE_CLKN[3:0]
PCIE_CLKP[3:0]
100 MHz
Differential Clocks supplied to 
external PCI express devices based 
on assertion of PCIE_CLKREQ[3:0]# 
inputs
USB PHY
USB_ULPI_REFCLK
19.2 MHz
Clock for USB devices
HDMI
DDI[1:0]_TXP/N[3] 25-148.5 MHz
Differential clock for HDMI devices
HDMI DDC
DDI[1:0]_DDCCLK
100 kHz
Clock for HDMI DDC devices