Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

835

19

0b

RW

This bit when set will cause all enabled Display 

and overlay planes that are assigned to this pipe to be disabled by overriding the 

current setting of the plane enable bit, at the next VBLANK. Timing signals continue as 

they were but the screen becomes blank. Setting the bit back to a zero will then allow 

the display and overlay planes to resume on the following VBLANK. 

0 = Normal Operation 

1 = Planes assigned to this pipe are disabled.

18

0b

RW

This bit when set will cause all enabled cursor planes that are 

assigned to this pipe to be disabled by overriding the current setting of the plane enable 

bit, at the next VBLANK. Timing signals continue as they were but the cursor(s) no 

longer appear on the screen. Setting the bit back to a zero will then allow the cursor 

planes to resume on the following VBLANK. 

0 = Normal Operation 

1 = Planes assigned to this pipe are disabled.

17:16

0b

RW

These bits select how refresh rates 

are tied to big FIFO mode on pipe A. When they are set to anything other than 00, bits 

23:21 of this register must be programmed to 0xx. Switching between 01 and 10 

settings directly is not allowed. Software must program this field to 00 before switching. 

Software is responsible for enabling this mode only for integrated dispay panels that 

support corresponding mode. 

00 Default no dynamic refresh rate change enabled. Software control only. 

01 Progressive-to-progressive refresh rate change enabled and tied to big FIFO mode. 

Pixel clock values set in FPA0/FPA1 settings in the DPLLA control register and FPA0/FPA1 

divider registers. FPA0 is tied to non-big-FIFO mode 

10 Progressive-to-interlaced refresh rate change enabled and tied to big FIFO mode. 

Pixel clock value does not change in this case. Scaling must be disabled in this mode. 

Uses programmable VS shift 

11 Reserved

15

0b

RW

R_CORRECTION_COEFFICIENTS_ARE_DISABLED_: 
•

1 = Color Correction Coefficients are enabled to perform color correction 

•

0 = Color Correction Coefficients are disabled 

14

0b

RW

This bit selects the software 

controlled progressive to progressive power saving mode (software controlled DRRS). 

Hardware Controlled Refresh Rate Select must be disabled when enabling this. Link and 

data M/N 1 values are used for normal settings, M/N 2 values are used for low power 

settings.  

0 Normal progressive refresh rate (default) 

1 Low Power progressive refresh rate

13

0b

RW

[DevVLVP]: This bit is used to select the color range of RBG 

outputs.  

0 = Apply full 0-255 color range to the output (Default) 

1 = Apply 16-235 color range to the output

12

0b

RW

This bit controls the blending order of the sprite planes for S3D 

support: 

0 = Sprite A first. The first line or pixel comes from Sprite A (default) 

1 = Sprite B first. The first line or pixel comes from Sprite B

11:10

0b

RW

These bits control the Sprite A/B 

interleaving format in S3D mode 

00 = No interleaving  

01 = Line interleaving 

10 = Pixel interleaving 

11 = Reserved

9:8

0b

RW

[DevCDV, DevVLVP] MBZ Scrambling enable [DevCTG]: This bit enables 

scrambling for DisplayPort. Software must set this bit appropriately when enabling a 

DisplayPort output.  

00 = Scrambling disabled (Default) 

01 = Scrambling enabled, no SR after initialization at loop 2 of training 

10 - RESERVED  

11 = Scrambling and SR enabled. Scrambling is reset every 512 BS symbols.